MT48H8M32LFB5-6:H TR Micron Technology Inc, MT48H8M32LFB5-6:H TR Datasheet - Page 38

• Manufacturer Part Number: MT48H8M32LFB5-6:H TR
• Description: IC SDRAM 256MBIT 166MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-6:H TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Initialization
PDF: 09005aef834c13d2
256mb_mobile_sdram_y36n.pdf - Rev. I 11/09 EN
Low-power SDRAM devices must be powered up and initialized in a predefined man-
ner. Using initialization procedures other than those specified may result in undefined
operation. After power is simultaneously applied to V
ble (a stable clock is defined as a signal cycling within timing constraints specified for
the clock ball), the device requires a 100μs delay prior to issuing any command other
than a COMMAND INHIBIT or NOP. Starting at some point during this 100μs period
and continuing at least through the end of this period, COMMAND INHIBIT or NOP
commands should be applied.
After the 100μs delay is satisfied by issuing at least one COMMAND INHIBIT or NOP
command, a PRECHARGE command must be issued. All banks must then be pre-
charged, which places the device in the all banks idle state.
When in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO
REFRESH cycles are complete, the device is ready for mode register programming. Be-
cause the mode register powers up in an unknown state, it should be loaded prior to
issuing any operational command.
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
38
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DD
and V
©2008 Micron Technology, Inc. All rights reserved.
DDQ
and the clock is sta-
Initialization