MT48H8M32LFB5-6:H TR Micron Technology Inc, MT48H8M32LFB5-6:H TR Datasheet - Page 21

• Manufacturer Part Number: MT48H8M32LFB5-6:H TR
• Description: IC SDRAM 256MBIT 166MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-6:H TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 11: AC Functional Characteristics
Notes 1–5 apply to all parameters and conditions
PDF: 09005aef834c13d2
256mb_mobile_sdram_y36n.pdf - Rev. I 11/09 EN
Parameter
Last data-in to burst STOP command
READ/WRITE command to READ/WRITE command
Last data-in to new READ/WRITE command
CKE to clock disable or power-down entry mode
Data-in to ACTIVE command
Data-in to PRECHARGE command
DQM to input data delay
DQM to data mask during WRITEs
DQM to data High-Z during READs
WRITE command to input data delay
LOAD MODE REGISTER command to ACTIVE or REFRESH command
CKE to clock enable or power-down exit mode
Last data-in to PRECHARGE command
Data-out High-Z from PRECHARGE command
Notes:
1. A full initialization sequence is required before proper device operation is ensured.
2. The minimum specifications are used only to indicate cycle time at which proper opera-
3. In addition to meeting the transition rate specification, the clock and CKE must transit
4. Outputs measured for 1.8V at 0.9V with equivalent load:
5. AC timing tests have V
6. The clock frequency must remain constant (stable clock is defined as a signal cycling with-
7.
8. This device requires 8192 AUTO REFRESH cycles every 64ms (
9. AC characteristics assume
tion over the full temperature range (–40˚C ≤ T
between V
Test loads with full DQ driver strength. Performance will vary with actual system DQ bus
capacitive loading, termination, and programmed drive strength.
input transition time is longer than
V
in timing constraints specified for the clock ball) during access or precharge states
(READ, WRITE, including
the data rate.
t
reference to V
uted AUTO REFRESH command every 7.8125μs meets the refresh requirement and en-
sures that each row is refreshed. Alternatively, 8192 AUTO REFRESH commands can be
issued in a burst at the minimum cycle rate (
timing must be derated. Input setup times require an additional 50ps for each 100 mV/
Q
HZ defines the time at which the output achieves the open circuit condition; it is not a
IH,min
and no longer at the V
IH
and V
Electrical Specifications – AC Operating Conditions
OH
20pF
or V
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
IL
(or between V
OL
IL
. The last valid data element will meet
CL = 3
CL = 2
and V
t
WR, and PRECHARGE commands). CKE may be used to reduce
21
t
T = 1ns. For command and address input slew rates <0.5V/ns,
IH/2
IH
with timing referenced to V
crossover point.
IL
Symbol
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Tmax, then the timing is referenced at V
t
t
t
t
and V
t
t
t
t
CKED
t
t
t
t
DQM
DWD
t
t
DQD
MRD
ROH
DQZ
BDL
CCD
CDL
DAL
PED
RDL
DPL
IH
t
) in a monotonic manner.
RFC), one time for every 64ms.
A
≤ +85˚C industrial temperature) is ensured.
-6
1
1
1
1
5
2
0
0
2
0
2
1
2
3
2
-75
t
IH/2
1
1
1
1
5
2
0
0
2
0
2
1
2
3
2
REF). Providing a distrib-
©2008 Micron Technology, Inc. All rights reserved.
t
OH before going High-Z.
= crossover point. If the
Unit
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
IL,max
Notes
14, 16
15, 16
15, 16
12
12
12
13
12
12
12
12
13
12
and