dsPIC33FJ09GS302-E/SS Microchip Technology, dsPIC33FJ09GS302-E/SS Datasheet - Page 8

• Manufacturer Part Number: dsPIC33FJ09GS302-E/SS
• Description: Digital Signal Processors & Controllers - DSP, DSC 40 MIPS 9 KB FL 1024Bytes RAM SMPS
• Manufacturer: Microchip Technology

Specifications of dsPIC33FJ09GS302-E/SS

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 9 KB
• Data Ram Size: 1 KB
• Device Million Instructions Per Second: 40 MIPs
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 125 C
• Package / Case: SSOP-28
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C

dsPIC33F DEVICES WITH VOLATILE CONFIGURATION BITS
3.3
After entering into ICSP mode, the CPU is Idle.
Execution of the CPU is governed by an internal state
machine. A 4-bit control code is clocked in using PGECx
and PGEDx and this control code is used to command
the CPU (see
The SIX control code is used to send instructions to the
CPU for execution and the REGOUT control code is
used to read data out of the device via the VISI register.
TABLE 3-1:
FIGURE 3-3:
FIGURE 3-4:
DS70659B-page 8
Control Code
0000b
0001b
0010b-1111b N/A
PGECx
PGEDx
P2
Fetch SIX Control Code
4-bit
Execute PC – 1,
1
0
ICSP Operation
PGECx
PGEDx
2
0
P3
Table
P2
Fetch SIX Control Code
3
0
Execute PC – 1,
SIX
REGOUT
Mnemonic
1
0
CPU CONTROL CODES IN
ICSP™ MODE
4
0
3-1).
2
0
5
0
SIX SERIAL EXECUTION
PROGRAM ENTRY AFTER RESET
P3
0
6
3
0
0
7
4
0
Shift in 24-bit instruction
and execute.
Shift out the VISI
register.
Reserved.
P4
LSB X
0
8
1
Description
0
9
2
P1B
P4
LSB X
X
P1A
3
1
PGEDx = Input
X
P1
4
2
P1B
X
X
P1A
5
3
X
PGEDx = Input
X
6
P1
4
24-bit Instruction Fetch
X
X
7
5
X
X
8
6
24-bit Instruction Fetch
X
X
17
7
3.3.1
The SIX control code allows execution of assembly
instructions. When the SIX code is received, the CPU is
suspended for 24 clock cycles, as the instruction is then
clocked into the internal buffer. Once the instruction is
shifted in, the state machine allows it to be executed over
the next four clock cycles. While the received instruction
is executed, the state machine simultaneously shifts in
the next 4-bit command (see
X
X
18 19 20 21 22
Note 1: Coming out of the ICSP entry sequence,
8
X
X
17
X
X
18 19 20 21 22
X
X
SIX SERIAL INSTRUCTION
EXECUTION
the first 4-bit control code is always
forced to SIX and a forced NOP instruc-
tion is executed by the CPU. Five addi-
tional PGECx clocks are needed on
start-up, thereby resulting in a 9-bit SIX
command instead of the normal 4-bit SIX
command. After the forced SIX is
clocked in, ICSP operation resumes as
normal (the next 24 clock cycles load the
first instruction word to the CPU). See
Figure 3-4
X
X
X MSB
X
23 24
X
for details.
© 2011 Microchip Technology Inc.
X MSB
Execute 24-bit Instruction,
Fetch Next Control Code
P4a
23 24
Figure
1
0
Execute 24-bit Instruction,
Fetch Next Control Code
P4a
3-3).
2
0
1
3
0
0
4
2
0
0
3
0
4
0