dsPIC33FJ09GS302-E/SS Microchip Technology, dsPIC33FJ09GS302-E/SS Datasheet - Page 12

• Manufacturer Part Number: dsPIC33FJ09GS302-E/SS
• Description: Digital Signal Processors & Controllers - DSP, DSC 40 MIPS 9 KB FL 1024Bytes RAM SMPS
• Manufacturer: Microchip Technology

Specifications of dsPIC33FJ09GS302-E/SS

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 9 KB
• Data Ram Size: 1 KB
• Device Million Instructions Per Second: 40 MIPs
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 125 C
• Package / Case: SSOP-28
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C

dsPIC33F DEVICES WITH VOLATILE CONFIGURATION BITS
3.5
The procedure for erasing program memory (including
code-protect bits) is shown in
setting NVMCON to 0x404F, initializing the TBLPAG
register to 0x00, and then executing the programming
cycle. For page erase operations, the NVMCON value
should be modified suitably, according to
Table 3-4
Erasing program memory.
TABLE 3-4:
DS70659B-page 12
4-bit Control
Step 1: Exit the Reset vector.
Step 2: Set the NVMCON to erase all program memory.
Step 3: Initiate the TBLPAG register for program memory.
Step 4: Initiate the erase cycle.
Step 5: Wait for Bulk Erase operation to complete to ensure that the WR bit is clear.
Code
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
—
Erasing Program Memory
illustrates the ICSP programming process for
SERIAL INSTRUCTION EXECUTION FOR ERASING PROGRAM MEMORY
040200
040200
000000
2404FA
883B0A
200001
880191
A8E761
000000
000000
000000
000000
(Hex)
Data
—
Figure
GOTO
GOTO
NOP
MOV
MOV
MOV
MOV
BSET
NOP
NOP
NOP
NOP
Externally time ‘P11’ + ‘P10’ ms (see
Timing
complete.
3-6. It consists of
Table
Requirements”) to allow sufficient time for the Bulk Erase operation to
0x200
#0x404F, W10
W10, NVMCON
#0x00, W1
W1, TBLPAG
NVMCON, #WR
0x200
3-2.
FIGURE 3-6:
Description
Section 9.0 “AC/DC Characteristics and
Initialize the TBLPAG register to 0x00
Write 0x404F to NVMCON SFR
Set the WR bit to Initiate Erase
Delay P11 + P10 Time
PROGRAM MEMORY
ERASE FLOW
© 2011 Microchip Technology Inc.
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