dsPIC33FJ09GS302-E/SS Microchip Technology, dsPIC33FJ09GS302-E/SS Datasheet - Page 34

• Manufacturer Part Number: dsPIC33FJ09GS302-E/SS
• Description: Digital Signal Processors & Controllers - DSP, DSC 40 MIPS 9 KB FL 1024Bytes RAM SMPS
• Manufacturer: Microchip Technology

Specifications of dsPIC33FJ09GS302-E/SS

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 9 KB
• Data Ram Size: 1 KB
• Device Million Instructions Per Second: 40 MIPs
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 125 C
• Package / Case: SSOP-28
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C

dsPIC33F DEVICES WITH VOLATILE CONFIGURATION BITS
6.0
6.1
The programmer and programming executive have a
master-slave relationship, where the programmer is
the master programming device and the programming
executive is the slave.
All communication is initiated by the programmer in the
form of a command. Only one command at a time can
be sent to the programming executive. In turn, the
programming executive only sends one response to
the programmer after receiving and processing a
command. The programming executive command set
is described in
Commands”. The response set is described in
Section 6.3 “Programming Executive
6.1.1
The Enhanced ICSP interface is a 2-wire SPI imple-
mented using the PGECx and PGEDx pins. The PGECx
pin is used as a clock input pin and the clock source
must be provided by the programmer. The PGEDx pin is
used for sending command data to and receiving
response data from the programming executive.
FIGURE 6-2:
DS70659B-page 34
Note:
Note 1:
PGECx
PGEDx
THE PROGRAMMING
EXECUTIVE
Programming Executive
Communication
COMMUNICATION INTERFACE
AND PROTOCOL
For Enhanced ICSP, all serial data is
transmitted on the falling edge of PGECx
and latched on the rising edge of PGECx.
All data transmissions are sent to the Most
Significant bit first using 16-bit mode (see
Figure
Section 6.2 “Programming Executive
A delay of 25 ms is required between commands.
MSB X X X LSB
1
6-1).
Last Command Word
PGECx = Input
PGEDx = Input
2
Host Transmits
PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL
15 16
P8
Responses”.
Programming Executive
PGECx = Input (Idle)
PGEDx = Output
P9a
Processes Command
1
P9b
0
FIGURE 6-1:
Since a 2-wire SPI is used, and data transmissions are
bidirectional, a simple protocol is used to control the
direction of PGEDx. When the programmer completes
a command transmission, it releases the PGEDx line
and allows the programming executive to drive this line
high. The programming executive keeps the PGEDx
line high to indicate that it is processing the command.
After the programming executive has processed the
command, it brings PGEDx low (P9b) to indicate to the
programmer that the response is available to be
clocked out. The programmer can begin to clock out
the response after maximum wait (P9b) and it must
provide the necessary amount of clock pulses to
receive the entire response from the programming
executive.
After the entire response is clocked out, the
programmer should terminate the clock on PGECx until
it is time to send another command to the programming
executive. This protocol is illustrated in
6.1.2
In Enhanced ICSP mode, the dsPIC33F family devices
operate from the Fast Internal RC oscillator, which has
a nominal frequency of 7.3728 MHz. This oscillator
frequency yields an effective system clock frequency of
1.8432 MHz. To ensure that the programmer does not
clock too fast, it is recommended that a 1.85 MHz clock
be provided by the programmer.
PGECx
PGEDx
1
P1B
MSb
P1A
2
1
MSB X X X LSB
SPI RATE
2
14 13 12
3
P1
Host Clocks Out Response
4
15 16
5
PGECx = Input
PGEDx = Output
PROGRAMMING
EXECUTIVE SERIAL
TIMING
11
6
© 2011 Microchip Technology Inc.
11
...
1
MSB X X X LSB
P2
12
5
2
13
4
15 16
14
3
Figure
P3
15 16
2
1
6-2.
LSb