dsPIC33FJ09GS302-E/SS Microchip Technology, dsPIC33FJ09GS302-E/SS Datasheet - Page 24

• Manufacturer Part Number: dsPIC33FJ09GS302-E/SS
• Description: Digital Signal Processors & Controllers - DSP, DSC 40 MIPS 9 KB FL 1024Bytes RAM SMPS
• Manufacturer: Microchip Technology

Specifications of dsPIC33FJ09GS302-E/SS

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 9 KB
• Data Ram Size: 1 KB
• Device Million Instructions Per Second: 40 MIPs
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 125 C
• Package / Case: SSOP-28
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C

dsPIC33F DEVICES WITH VOLATILE CONFIGURATION BITS
4.4
As illustrated in
Program/Verify mode requires three steps:
1.
2.
3.
The programming voltage applied to MCLR is V
which is essentially V
no minimum time requirement for holding at V
V
before presenting the key sequence on PGEDx.
The key sequence is a specific 32-bit pattern,
‘0100 1101 0100 0011 0100 1000 0101 0000’
(more easily remembered as 0x4D434850 in hexa-
decimal format). The device will enter Program/Verify
mode only if the key sequence is valid. The Most
Significant bit (MSb) of the most significant nibble must
be shifted in first.
Once the key sequence is complete, V
applied to MCLR and held at that level for as long as
Program/Verify mode is to be maintained. An interval
time of at least P19, and P1 * 5, must elapse before
presenting data on PGEDx. Signals appearing on
PGEDx before this time has elapsed will not be
interpreted as valid.
On successful entry, the program memory can be
accessed and programmed in serial fashion. While in
the Program/Verify mode, all unused I/Os are placed in
the high-impedance state.
FIGURE 4-3:
DS70659B-page 24
IH
PGEDx
PGECx
MCLR
is removed, an interval of at least P18 must elapse
The MCLR pin is briefly driven high then low.
A 32-bit key sequence is clocked into PGEDx.
MCLR is then driven high within a specified
period of time and held.
V
DD
Entering Enhanced ICSP Mode
P14
P6
Figure
DD
P21
ENTERING ENHANCED ICSP™ MODE
4-3, entering Enhanced ICSP
in dsPIC33F devices. There is
P18
b31
0
V
IH
b30
1
Program/Verify Entry Code = 0x4D434850
b29
0
IH
P1A
b28
must be
IH
0
. After
P1B
b27
IH
1
,
...
b3
4.5
The term “Blank Check” implies verifying that the
device has been successfully erased and has no
programmed memory locations. A blank or erased
memory location is always read as ‘1’.
The Device ID registers (0xFF0000:0xFF0002) can be
ignored by the Blank Check since this region stores
device information that cannot be erased. Additionally,
all unimplemented memory space should be ignored
from the Blank Check.
The QBLANK command is used for the Blank Check. It
determines if the code memory is erased by testing
these memory regions. A ‘BLANK’ or ‘NOT BLANK’
response is returned. If it is determined that the device
is not blank, it must be erased before attempting to
program the chip.
0
b2
0
Blank Check
b1
0
V
IH
b0
0
P19
© 2011 Microchip Technology Inc.
P7
P1
·
5