dsPIC33FJ09GS302-E/SS Microchip Technology, dsPIC33FJ09GS302-E/SS Datasheet - Page 27

• Manufacturer Part Number: dsPIC33FJ09GS302-E/SS
• Description: Digital Signal Processors & Controllers - DSP, DSC 40 MIPS 9 KB FL 1024Bytes RAM SMPS
• Manufacturer: Microchip Technology

Specifications of dsPIC33FJ09GS302-E/SS

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 9 KB
• Data Ram Size: 1 KB
• Device Million Instructions Per Second: 40 MIPs
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 125 C
• Package / Case: SSOP-28
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C

5.0
5.1
If it is determined that the programming executive is not
present in executive memory (as described in
Section 4.2 “Confirming the Presence of the
Programming
executive must be programmed to executive memory.
Figure 5-1
programming
executive memory. First, ICSP mode must be entered
and
programming executive is programmed and verified.
Lastly ICSP mode is exited.
FIGURE 5-1:
© 2011 Microchip Technology Inc.
Note:
dsPIC33F DEVICES WITH VOLATILE CONFIGURATION BITS
executive
PROGRAMMING THE
PROGRAMMING EXECUTIVE
TO MEMORY
Overview
The Programming Executive (PE) can be
located within the following folder within
your installation of MPLAB
...\Microchip\MPLAB IDE\REAL ICE,
and then selecting the Hex PE file,
RIPE_01d_xxxxxx.hex.
shows
the
Programming Executive
Programming Executive
Executive”),
memory
Enter ICSP mode
Erase Executive
Exit ICSP mode
Read/Verify the
Program the
the
programming
HIGH-LEVEL
PROGRAMMING
EXECUTIVE
PROGRAMMING FLOW
Memory
Start
End
high
is
erased,
the
level
®
executive
IDE:
programming
process
then
into
the
of
5.2
The procedure for erasing executive memory is similar
to that of erasing program memory and is shown in
Figure
initializing the TBLPAG register to the beginning of
executive memory; 0x80, and then executing the
programming cycle.
Table 5-1
Erasing executive memory.
FIGURE 5-2:
Note:
5-2. It consists of setting NVMCON to 0x404F,
Erasing Executive Memory
illustrates the ICSP programming process for
Initialize the TBLPAG register to 0x80
The
always
programmed, as described in
Write 0x404F to NVMCON SFR
Set the WR bit to Initiate Erase
Delay P11 + P10 Time
programming
be
ERASE FLOW
Start
End
erased
executive
DS70659B-page 27
before
Figure
it
must
5-1.
is