dsPIC33FJ09GS302-E/SS Microchip Technology, dsPIC33FJ09GS302-E/SS Datasheet - Page 26

• Manufacturer Part Number: dsPIC33FJ09GS302-E/SS
• Description: Digital Signal Processors & Controllers - DSP, DSC 40 MIPS 9 KB FL 1024Bytes RAM SMPS
• Manufacturer: Microchip Technology

Specifications of dsPIC33FJ09GS302-E/SS

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 9 KB
• Data Ram Size: 1 KB
• Device Million Instructions Per Second: 40 MIPs
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 125 C
• Package / Case: SSOP-28
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C

dsPIC33F DEVICES WITH VOLATILE CONFIGURATION BITS
4.7
Configuration bits are programmed one at a time using
the PROGW command. This command specifies the
configuration data and address. When Configuration
bits are programmed, any unimplemented bits must be
programmed with a ‘1’.
Multiple PROGW commands are required to program all
Configuration bits. A flowchart for Configuration bit
programming is shown in
FIGURE 4-6:
DS70659B-page 26
ConfigAddress + 2
ConfigAddress =
Configuration Bit Programming
No
CONFIGURATION BIT
PROGRAMMING FLOW
PROGW response
Figure
Configuration
Send PROGW
Command
PASS?
Byte?
Start
Last
End
Is
4-6.
Yes
Yes
Report Error
Failure
No
4.8
After code memory is programmed, the contents of
memory can be verified to ensure that programming
was successful. Verification requires code memory to
be read back and compared against the copy held in
the programmer’s buffer.
The READP command can be used to read back all the
programmed code memory and Configuration words.
Alternatively, you can have the programmer perform
the verification after the entire device is programmed,
using a checksum computation.
See
information on calculating the checksum.
4.9
Exiting Program/Verify mode is done by removing V
from MCLR, as illustrated in
requirement for exit is that an interval P16 should
elapse between the last clock and program signals on
PGECx and PGEDx before removing V
FIGURE 4-7:
Section 8.0 “Checksum Computation”
MCLR
V
PGEDx
PGECx
DD
Programming Verification
Exiting Enhanced ICSP Mode
PGEDx = Input
EXITING ENHANCED
ICSP™ MODE
© 2011 Microchip Technology Inc.
V
P16
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Figure
P17
V
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4-7. The only
.
for more
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