dsPIC33FJ09GS302-E/SS Microchip Technology, dsPIC33FJ09GS302-E/SS Datasheet - Page 7

• Manufacturer Part Number: dsPIC33FJ09GS302-E/SS
• Description: Digital Signal Processors & Controllers - DSP, DSC 40 MIPS 9 KB FL 1024Bytes RAM SMPS
• Manufacturer: Microchip Technology

Specifications of dsPIC33FJ09GS302-E/SS

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 9 KB
• Data Ram Size: 1 KB
• Device Million Instructions Per Second: 40 MIPs
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 125 C
• Package / Case: SSOP-28
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C

3.2
As illustrated in
Verify mode requires three steps:
1.
2.
3.
The programming voltage applied to MCLR is V
which is essentially V
devices. There is no minimum time requirement for
holding at V
least P18 must elapse before presenting the key
sequence on PGEDx.
FIGURE 3-2:
© 2011 Microchip Technology Inc.
PGEDx
PGECx
Note 1: If a capacitor is present on the MCLR pin,
MCLR
dsPIC33F DEVICES WITH VOLATILE CONFIGURATION BITS
MCLR is briefly driven high then low (P21)
A 32-bit key sequence is clocked into PGEDx.
MCLR is then driven high within a specified
period of time ‘P19’ and held.
V
DD
Entering ICSP Mode
P14
IH
the high time for entering ICSP mode can
vary.
. After V
P6
Figure
P21
ENTERING ICSP™ MODE
IH
DD
3-2, entering ICSP Program/
is removed, an interval of at
P18
in the case of dsPIC33F
b31
0
V
IH
b30
1
Program/Verify Entry Code = 0x4D434851
b29
0
b28
P1A
0
(1)
P1B
.
b27
IH
1
,
...
b3
The key sequence is a specific 32-bit pattern,
‘0100 1101 0100 0011 0100 1000 0101 0001’
(more
hexadecimal). The device will enter Program/Verify
mode only if the sequence is valid. The Most Significant
bit of the most significant nibble must be shifted in first.
Once the key sequence is complete, V
applied to MCLR and held at that level for as long as
Program/Verify mode is to be maintained. An interval of
at least time P19, and P1 * 5, must elapse before pre-
senting data on PGEDx. Signals appearing on PGEDx
before this time has elapsed will not be interpreted as
valid.
On successful entry, the program memory can be
accessed and programmed in serial fashion. While in
ICSP mode, all unused I/Os are placed in the
high-impedance state.
0
b2
0
easily
b1
0
V
IH
b0
1
remembered
P19
P7
as
P1
·
5
0x4D434851
DS70659B-page 7
IH
must be
in