dsPIC33FJ09GS302-E/SS Microchip Technology, dsPIC33FJ09GS302-E/SS Datasheet - Page 47

• Manufacturer Part Number: dsPIC33FJ09GS302-E/SS
• Description: Digital Signal Processors & Controllers - DSP, DSC 40 MIPS 9 KB FL 1024Bytes RAM SMPS
• Manufacturer: Microchip Technology

Specifications of dsPIC33FJ09GS302-E/SS

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 9 KB
• Data Ram Size: 1 KB
• Device Million Instructions Per Second: 40 MIPs
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 125 C
• Package / Case: SSOP-28
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C

TABLE 9-1:
© 2011 Microchip Technology Inc.
Standard Operating Conditions
Operating Temperature: -40ºC to +85ºC. Programming at +25ºC is recommended.
P9b
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P21
Param.
No.
Note 1: V
dsPIC33F DEVICES WITH VOLATILE CONFIGURATION BITS
2: Time depends on the FRC accuracy and the value of the FRC Oscillator tuning register. Refer to the
3: This time applies to both Program Memory words and Configuration words.
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
DLY
DLY
DLY
DLY
DLY
R
VALID
DLY
HLD
KEY
KEY
MCLRH
±0.3V of V
“Electrical Characteristics” section in the specific device data sheet.
DD
5
6
7
8
9
10 Delay between Last PGECx ↓ and MCLR ↓
3
1
2
must also be supplied to the AV
AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS (CONTINUED)
Delay between PGEDx ↓ by Programming
Executive to PGEDx Released by
Programming Executive
PGECx Low Time After Programming
Bulk Erase Time
Page Erase Time
Word Programming Time
MCLR Rise Time to Enter ICSP mode
Data Out Valid from PGECx ↑
MCLR ↓ to V
Delay from First MCLR ↓ to First PGECx ↑ for
Key Sequence on PGEDx
Delay from Last PGECx ↓ for Key Sequence on
PGEDx to Second MCLR ↑
MCLR High Time
DD
and V
DD
SS
↓
Characteristic
, respectively.
DD
pins during programming. AV
Min.
20.1
47.9
400
200
100
15
10
25
—
—
0
1
Max.
26.5
240
500
1.0
23
—
—
—
—
—
—
—
DD
and AV
Units
ms See Note 2
ms See Note 2
ms
μs
ns
μs
μs
ns
ns
ns
μs
s
SS
See Note 2 and Note 3
should always be within
Conditions
DS70659B-page 47
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