cp3cn17 National Semiconductor Corporation, cp3cn17 Datasheet - Page 97

• Manufacturer Part Number: cp3cn17
• Description: Reprogrammable Connectivity Processor With Can Interface
• Manufacturer: National Semiconductor Corporation

15.10.12 CAN Interrupt Clear Register (CICLR)
The CICLR register bits individually clear CAN interrupt
pending flags caused by the message buffers and from the
Error Management Logic. Do not modify this register with in-
structions that access the register as a read-modify-write
operand, such as the bit manipulation instructions.
EICLR
ICLR
15.10.13 CAN Interrupt Code Enable Register (CICEN)
The CICEN register controls whether the interrupt pending
flag in the CIPND register is translated into the Interrupt
Code field of the CSTPND register. All interrupt requests,
CAN error, and message buffer interrupts can be enabled/
disabled separately for the interrupt code indication field.
EICEN
ICEN
EICLR
EICEN
15
15
14
14
The Error Interrupt Clear bit is used to clear
the EIPND bit.
0 – The EIPND bit is unaffected by writing 0.
1 – The EIPND bit is cleared by writing 1.
The Buffer Interrupt Clear bits are used to
clear the IPND bits.
0 – The corresponding IPND bit is unaffected
0 – The corresponding IPND bit is cleared by
The Error Interrupt Code Enable bit controls
encoding for error interrupts.
0 – Error interrupt pending is not indicated in
1 – Error interrupt pending is indicated in the
The Buffer Interrupt Code Enable bits control
encoding for message buffer interrupts.
0 – Message buffer interrupt pending is not
1 – Message buffer interrupt pending is indi-
by writing 0.
writing 1.
the interrupt code.
interrupt code.
indicated in the interrupt code.
cated in the interrupt code.
R/W
W
0
0
ICLR
ICEN
0
0
97
15.10.14 CAN Status Pending Register (CSTPND)
The CSTPND register holds the status of the CAN Node
and the Interrupt Code.
NS
IRQ/IST
15
Reserved
The CAN Node Status field indicates the sta-
tus of the CAN node as shown in Table 48.
The IRQ bit and IST field indicate the interrupt
source of the highest priority interrupt current-
ly pending and enabled in the CICEN register.
Table 49 shows the several interrupt codes
when the encoding for all interrupt sources is
enabled (CICEN = FFFFh).
Table 49 Highest Priority Interrupt Code
IRQ
000
010
011
10X
11X
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
NS
8
Table 48 CAN Node Status
7
IST3:0
0000
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
NS
R
0
5
Error Warning Level
Error Passive
Node Status
IRQ
Error Active
Not Active
No interrupt request
4
Bus Off
CAN Interrupt
Error interrupt
Request
Buffer 10
Buffer 11
Buffer 12
Buffer 13
Buffer 14
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Buffer 0
Buffer 1
Buffer 2
Buffer 3
Buffer 4
Buffer 5
Buffer 6
Buffer 7
Buffer 8
Buffer 9
3
IST
0