cp3cn17 National Semiconductor Corporation, cp3cn17 Datasheet - Page 56

• Manufacturer Part Number: cp3cn17
• Description: Reprogrammable Connectivity Processor With Can Interface
• Manufacturer: National Semiconductor Corporation

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ACE1
ACE2
POR
11.8.2
The PRSFC register is a byte-wide read/write register that
holds the 4-bit clock divisor used to generate the high-fre-
quency clock. In addition, the upper three bits are used to
control the operation of the PLL. The register is initialized to
4Fh at reset (except in PROG mode
FCDIV
MODE
Res
7
High Frequency Clock Prescaler Register
(PRSFC)
6
When the Auxiliary Clock Enable bit is set and
a stable Main Clock is provided, the Auxiliary
Clock 1 prescaler is enabled and generates
the first Auxiliary Clock. When the ACE1 bit is
clear or the Main Clock is not stable, Auxiliary
Clock 1 is stopped. After reset this bit is clear.
0
1
When the Auxiliary Clock Enable 2 bit is set
and a stable Main Clock is provided, the Aux-
iliary Clock 2 prescaler is enabled and gener-
ates Auxiliary Clock 2. When the ACE2 bit is
clear or the Main Clock is not stable, the Aux-
iliary Clock 2 is stopped. Auxiliary Clock 2 is
used as the clock input for the CVSD/PCM
transcoder. After reset this bit is clear.
0
1
Power-On-Reset - The Power-On-Reset bit is
set when a power-turn-on condition has been
detected. This bit can only be cleared by soft-
ware, not set. Writing a 1 to this bit will be ig-
nored, and the previous value of the bit will be
unchanged.
0
1
The Fast Clock Divisor specifies the divisor
used to obtain the high-frequency System
Clock from the PLL or Main Clock. The divisor
is (FCDIV + 1).
The PLL MODE field specifies the operation
mode of the on-chip PLL. After reset the
MODE bits are initialized to 100b, so the PLL
is configured to generate a 48-MHz clock.
This register must not be modified when the
System Clock is derived from the PLL Clock.
The System Clock must be derived from the
MODE
–
–
–
–
–
–
Auxiliary Clock 1 is stopped.
Auxiliary Clock 1 is active if the Main
Clock is stable.
Auxiliary Clock 2 is stopped.
Auxiliary Clock 2 is active if the Main
Clock is stable.
Software cleared this bit.
Software has not cleared his bit since the
last reset.
4
3
.)
FCDIV
0
56
11.8.3
The PRSSC register is a byte-wide read/write register that
holds the clock divisor used to generate the Slow Clock from
the Main Clock. The register is initialized to B6h at reset.
SCDIV
11.8.4
The PRSAC register is a byte-wide read/write register that
holds the clock divisor values for prescalers used to gener-
ate the two auxiliary clocks from the Main Clock. The regis-
ter is initialized to FFh at reset.
ACDIV1
ACDIV2
7
7
Low Frequency Clock Prescaler Register
(PRSSC)
Auxiliary Clock Prescaler Register (PRSAC)
ACDIV2
low-frequency oscillator clock while the
MODE field is modified.
The Slow Clock Divisor field specifies a divi-
sor to be used when generating the Slow
Clock from the Main Clock. The Main Clock is
divided by a value of (2 × (SCDIV + 1)) to ob-
tain the Slow Clock. At reset, the SCDIV reg-
ister is initialized to B6h, which generates a
Slow Clock rate of 32786.89 Hz. This is about
0.5% faster than a Slow Clock generated from
an external 32768 Hz crystal network.
The Auxiliary Clock Divisor 1 field specifies
the divisor to be used for generating Auxiliary
Clock 1 from the Main Clock. The Main Clock
is divided by a value of (ACDIV1 + 1).
The Auxiliary Clock Divisor 2 field specifies
the divisor to be used for generating Auxiliary
Clock 2 from the Main Clock. The Main Clock
is divided by a value of (ACDIV2 + 1).
MODE2:0
000
001
010
011
100
101
110
111
4
SCDIV
Reserved
Reserved
Reserved
36 MHz
48 MHz
60 MHz
Reserved
Reserved
(from 12 MHz
input clock)
Frequency
3
Output
ACDIV2
Reserved
Reserved
Reserved
3× Mode
4× Mode
5× Mode
Reserved
Reserved
Description
0
0