cp3cn17 National Semiconductor Corporation, cp3cn17 Datasheet - Page 77

• Manufacturer Part Number: cp3cn17
• Description: Reprogrammable Connectivity Processor With Can Interface
• Manufacturer: National Semiconductor Corporation

15.2.7
The CAN prescaler (PSC) is shown is Figure 25. It divides
the CKI input clock by the value defined in the CTIM register.
The resulting clock is called time quanta clock and defines
the length of one time quantum (tq).
Please refer to CAN Timing Register (CTIM) on page 94 for
a detailed description of the CTIM register.
Note: PSC is the value of the clock prescaler. TSEG1 and
TSEG2 are the length of time segment 1 and 2 in time quan-
ta.
The resulting bus clock can be calculated by the equation:
The values of PSC, TSEG1, and TSEG2 are specified by
the contents of the registers PSC, TSEG1, and TSEG2 as
follows:
busclock
Clock Generator
Signal
Clock
=
CAN
Bus
------------------------------------------------------------------------------------ -
(
PSC
Signal
Clock
CAN
Bus
PREVIOUS
PREVIOUS
BIT
BIT
)x 1
PREVIOUS
PREVIOUS
(
BIT
BIT
+
TSEG1
A
A
CKI
A
A
Figure 24. Resynchronization (e < -SJW)
Figure 23. Resynchronization (e > SJW)
e
+
TSEG2
TSEG1
TSEG1
"NORMAL" BIT TIME
BIT TIME LENGTHENED BY SJW
BIT TIME SHORTENED BY SJW
)
TSEG1
TSEG1
"NORMAL" BIT TIME
77
15.3
The CAN module has access to 15 independent message
buffers, which are memory mapped in RAM. Each message
buffer consists of 8 different 16-bit RAM locations and can
be individually configured as a receive message buffer or as
a transmit message buffer.
A dedicated acceptance filtering procedure enables soft-
ware to configure each buffer to receive only a single mes-
sage ID or a group of messages. One buffer uses an
CKI
TSEG2
PSC = PSC[5:0] + 2
TSEG1 = TSEG1[3:0] + 1
TSEG2 = TSEG2[2:0] + 1
SJW
MESSAGE TRANSFER
÷
PSC
TSEG2
Figure 25. CAN Prescaler
TSEG2
TSEG2
Internal Time
Quanta Clock (1/tq)
NEXT BIT
e
÷
NEXT BIT
(1+TSEG1+TSEG2)
NEXT BIT
DS030
DS029
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Bit Rate
DS031