cp3cn17 National Semiconductor Corporation, cp3cn17 Datasheet - Page 57

• Manufacturer Part Number: cp3cn17
• Description: Reprogrammable Connectivity Processor With Can Interface
• Manufacturer: National Semiconductor Corporation

12.0 Power Management
The Power Management Module (PMM) improves the effi-
ciency of the CP3CN17 by changing the operating mode
(and therefore the power consumption) according to the re-
quired level of device activity. The device implements four
power modes:
Table 26 summarizes the differences between power
modes: the state of the high-frequency oscillator (on or off),
the System Clock source (clock used by most modules),
and the clock source used by the Timing and Watchdog
Module (TWM). The high-frequency oscillator generates the
12-MHz Main Clock, and the low-frequency oscillator gener-
ates a 32.768 kHz clock. The Slow Clock can be driven by
the 32.768 kHz clock or a scaled version of the Main Clock.
The low-frequency oscillator continues to operate in all four
modes and power must be provided continuously to the de-
vice power supply pins. In Halt mode, however, Slow Clock
does not toggle, and as a result, the TWM timer and Watch-
dog Module do not operate. In Power Save mode, the high-
frequency oscillator can be turned on or off under software
control, as long as the low-frequency oscillator is used to
drive Slow Clock.
12.1
In Active mode, the high-frequency oscillator is active and
generates the 12-MHz Main Clock. The 32.768 kHz oscilla-
tor is active and may be used to generate the Slow Clock.
The PLL can be active or inactive, as required. Most on-chip
modules are driven by the System Clock. The System Clock
can be the PLL Clock after a programmable divider or the
12-MHz Main Clock. The activity of peripheral modules is
controlled by their enable bits.
Power consumption can be reduced in this mode by selec-
tively disabling modules and by executing the WAIT instruc-
tion. When the WAIT instruction is executed, the CPU stops
executing new instructions until it receives an interrupt sig-
nal. After reset, the CP3CN17 is in Active Mode.
Active
Power Save On or Off
Idle
Halt
Active
Power Save
Idle
Halt
Mode
Table 26 Power Mode Operating Summary
ACTIVE MODE
On
Off
Off
High-Frequency
Oscillator
Main Clock Slow Clock
Slow Clock Slow Clock
None
None
System
Clock
Slow Clock
None
TWM Clock
57
12.2
In Power Save mode, Slow Clock is used as the System
Clock which drives the CPU and most on-chip modules. If
Slow Clock is driven by the 32.768 kHz oscillator and no on-
chip module currently requires the 12-MHz Main Clock, soft-
ware can disable the high-frequency oscillator to further re-
duce power consumption. Auxiliary Clocks 1 and 2 can be
turned off under software control before switching to a re-
duced power mode, or they may remain active as long as
Main Clock is also active. If the system does not require the
PLL output clock, the PLL can be disabled. Alternatively, the
Main Clock and the PLL can also be controlled by the Hard-
ware Clock Control function, if enabled. The clock architec-
ture is described in Section 11.0.
In Power Save mode, some modules are disabled or their
operation is restricted. Other modules, including the CPU,
continue to function normally, but operate at a reduced clock
rate. Details of each module’s activity in Power Save mode
are described in each module’s descriptions.
It is recommended to keep CPU activity at a minimum by ex-
ecuting the WAIT instruction to guarantee low power con-
sumption in the system.
12.3
In Idle mode, the System Clock is disabled and therefore the
clock is stopped to most modules of the device. The DHC
and DMC bits in the PMMCR register must be set before en-
tering this mode to disable the PLL and the high-frequency
oscillator. The low-frequency oscillator remains active. The
Power Management Module (PMM) and the Timing and
Watchdog Module (TWM) continue to operate off the Slow
Clock. Idle mode can only be entered from Active mode.
12.4
In Halt mode, all the device clocks, including the System
Clock, Main Clock, and Slow Clock, are disabled. The DHC
and DMC bits in the PMMCR register must be set before en-
tering this mode. The high-frequency oscillator and PLL are
off. The low-frequency oscillator continues to operate, how-
ever its circuitry is optimized to guarantee lowest possible
power consumption. This mode allows the device to reach
the absolute minimum power consumption without losing its
state (memory, registers, etc.). Halt mode can only be en-
tered from Active mode.
POWER SAVE MODE
IDLE MODE
HALT MODE
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