cp3cn17 National Semiconductor Corporation, cp3cn17 Datasheet - Page 145

• Manufacturer Part Number: cp3cn17
• Description: Reprogrammable Connectivity Processor With Can Interface
• Manufacturer: National Semiconductor Corporation

MASTER
NMATCH
STASTR
NEGACK
BER
The Master bit indicates that the module is
currently in master mode. It is set when a re-
quest for bus mastership succeeds. It is
cleared upon arbitration loss (BER is set) or
the recognition of a Stop Condition.
0 – Slave mode.
1 – Master mode.
The New match bit is set when the address
byte following a Start Condition, or repeated
starts, causes a match or a global-call match.
The NMATCH bit is cleared when written with
1. Writing 0 to NMATCH is ignored. If the
ACBCTL1.INTEN bit is set, an interrupt is sent
when this bit is set.
0 – No match.
1 – Match or global-call match.
The Stall After Start bit is set by the successful
completion of an address sending (i.e., a Start
Condition sent without a bus error, or negative
acknowledge), if the ACBCTL1.STASTRE bit
is set. This bit is ignored in slave mode. When
the STASTR bit is set, it stalls the bus by pull-
ing down the SCL line, and suspends any oth-
er action on the bus (e.g., receives first byte in
master receive mode). In addition, if the
ACBCTL1.INTEN bit is set, it also sends an
interrupt to the ICU. Writing 1 to the STASTR
bit clears it. It is also cleared when the module
is disabled. Writing 0 to the STASTR bit has
no effect.
0 – No stall after start condition.
1 – Stall after successful start.
The Negative Acknowledge bit is set by hard-
ware when a transmission is not acknowl-
edged on the ninth clock. (In this case, the
SDAST bit is not set.) Writing 1 to NEGACK
clears it. It is also cleared when the module is
disabled. Writing 0 to the NEGACK bit is ig-
nored.
0 – No transmission not acknowledged condi-
1 – Transmission not acknowledged.
The Bus Error bit is set by the hardware when
a Start or Stop Condition is detected during
data transfer (i.e., Start or Stop Condition dur-
ing the transfer of bits 2 through 8 and ac-
knowledge cycle), or when an arbitration
problem is detected. Writing 1 to the BER bit
clears it. It is also cleared when the module is
disabled. Writing 0 to the BER bit is ignored.
0 – No bus error occurred.
1 – Bus error occurred.
tion.
145
SDAST
SLVSTP
20.3.3
The ACBCST register is a byte-wide, read/write register that
maintains current ACB status. At reset and when the mod-
ule is disabled, the non-reserved bits of ACBCST are
cleared.
BUSY
Reserved TGSCL TSDA GCMTCH MATCH BB BUSY
7
6
ACB Control Status Register (ACBCST)
The SDA Status bit indicates that the SDA
data register is waiting for data (transmit, as
master or slave) or holds data that should be
read (receive, as master or slave). This bit is
cleared when reading from the ACBSDA reg-
ister during a receive, or when written to dur-
ing a transmit. When the ACBCTL1.START bit
is set, reading the ACBSDA register does not
clear the SDAST bit. This enables the ACB to
send a repeated start in master receive mode.
0 – ACB module is not waiting for data trans-
1 – ACB module is waiting for data to be load-
The Slave Stop bit indicates that a Stop Con-
dition was detected after a slave transfer (i.e.,
after a slave transfer in which MATCH or
GCMATCH is set). Writing 1 to SLVSTP clears
it. It is also cleared when the module is dis-
abled. Writing 0 to SLVSTP is ignored.
0 – No stop condition after slave transfer oc-
1 – Stop condition after slave transfer oc-
The BUSY bit indicates that the ACB module
is:
The BUSY bit is cleared by the completion of
any of the above states, and by disabling the
module. BUSY is a read only bit. It must al-
ways be written with 0.
0 – ACB module is not busy.
1 – ACB module is busy.
5
Generating a Start Condition
In Master mode (ACBST.MASTER is set)
In Slave mode (ACBCST.MATCH or
ACBCST.GCMTCH is set)
In the period between detecting a Start
and completing the reception of the ad-
dress byte. After this, the ACB either be-
comes not busy or enters slave mode.
fer.
ed or unloaded.
curred.
curred.
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