cp3cn17 National Semiconductor Corporation, cp3cn17 Datasheet - Page 126

• Manufacturer Part Number: cp3cn17
• Description: Reprogrammable Connectivity Processor With Can Interface
• Manufacturer: National Semiconductor Corporation

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Figure 60 shows a diagram of the interrupt sources and as-
sociated enable bits.
The interrupts can be individually enabled or disabled using
the Enable Transmit Interrupt (UETI), Enable Receive Inter-
rupt (UERI), and Enable Receive Error Interrupt (UEER)
bits in the UICTRL register.
A transmit interrupt is generated when both the UTBE and
UETI bits are set. To remove this interrupt, software must ei-
ther disable the interrupt by clearing the UETI bit or write to
the UTBUF register (which clears the UTBE bit).
A receive interrupt is generated on these conditions:
A flow control interrupt is generated when both the UDCTS
and the UEFCI bits are set. To remove this interrupt, soft-
ware must either disable the interrupt by clearing the UEFCI
bit or read the UICTRL register (which clears the UDCTS
bit).
In addition to the dedicated inputs to the ICU for UART in-
terrupts, the UART receive (RXD) and Clear To Send (CTS)
signals are inputs to the MIWU (see Section 13.0), which
can be programmed to generate edge-triggered interrupts.
18.2.8
The UART can operate with one or two DMA channels. Two
DMA channels must be used for processor-independent
full-duplex operation. Both receive and transmit DMA can
be enabled simultaneously.
If transmit DMA is enabled (the UETD bit is set), the UART
generates a DMA request when the UTBE bit changes state
from clear to set. Enabling transmit DMA automatically dis-
Both the URBF and UERI bits are set. To remove this in-
terrupt, software must either disable the interrupt by
clearing the UERI bit or read from the URBUF register
(which clears the URBF bit).
Both the UERR and the UEEI bits are set. To remove this
interrupt, software must either disable the interrupt by
clearing the UEEI bit or read the USTAT register (which
clears the UERR bit).
DMA Support
UDOE
UPE
UFE
Figure 60. UART Interrupts
UDCTS
UERR
URBF
UTBE
126
ables transmit interrupts, without regard to the state of the
UETI bit.
If receive DMA is enabled (the UERD bit is set), the UART
generates a DMA request when the URBF bit changes state
from clear to set. Enabling receive DMA automatically dis-
ables receive interrupts, without regard to the state of the
UERI bit. However, receive error interrupts should be en-
abled (the UEEI bit is set) to allow detection of receive errors
when DMA is used.
18.2.9
A line break is generated when the UBRK bit is set in the
UMDSL1 register. The TXD line remains low until the pro-
gram resets the UBRK bit.
A line break is detected if RXD remains low for 10 bit times
or longer after a missing stop bit is detected.
18.2.10 Parity Generation and Detection
Parity is only generated or checked with the 7-bit and 8-bit
data formats. It is not generated or checked in the diagnostic
loopback mode, the attention mode, or in normal mode with
the 9-bit data format. Parity generation and checking are en-
abled and disabled using the PEN bit in the UFRS register.
The UPSEL bits in the UFRS register are used to select
odd, even, or no parity.
UEFCI
UERI
UETI
UEEI
Break Generation and Detection
RX
Interrupt
TX
Interrupt
FC
Interrupt
DS066