cp3cn17 National Semiconductor Corporation, cp3cn17 Datasheet - Page 168

• Manufacturer Part Number: cp3cn17
• Description: Reprogrammable Connectivity Processor With Can Interface
• Manufacturer: National Semiconductor Corporation

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23.2.2
The I/O Control Register 1 (IO1CTL) is a word-wide read/
write register. The register controls the function of the I/O
pins TIO1 through TIO4 depending on the selected mode of
operation. The register is clear after reset.
CxEDG
PxPOL
P2POL
P4POL
15
7
I/O Control Register 1 (IO1CTL)
14
6
The Capture Edge Control field specifies the
polarity of a capture event and the reset of the
counter. The value of this three bit field has no
effect while operating in PWM mode.
The PWM Polarity bit selects the output polar-
ity. While operating in PWM mode the bit
specifies the polarity of the corresponding
PWM output (TIOx). Once a counter is
stopped, the output will assume the value of
PxPOL, i.e., its initial value. The PxPOL bit
has no effect while operating in capture mode.
0 – The PWM output goes high at the 00h to
1 – The PWM output goes low at the 00h to
C2EDG
C4EDG
CxEDG
000
001
010
011
100
101
110
111
01h transition of the counter and will go
low once the counter value matches the
duty cycle value.
01h transition of the counter and will go
high once the counter value matches the
duty cycle value.
12
4
Falling edge
Falling edge
Rising edge
Rising edge
Both edges
Both edges
Both edges
Both edges
Capture
P1POL
P3POL
11
3
10
2
Counter Reset
Falling edge
Rising edge
Both edges
C1EDG
C3EDG
Yes
Yes
No
No
No
0
8
168
23.2.3
The IO2CTL register is a word-wide read/write register. The
register controls the functionality of the I/O pins TIO5
through TIO8 depending on the selected mode of operation.
The register is cleared at reset.
The functionality of the bit fields of the IO2CTL register is
identical to the ones described in the IO1CTL register sec-
tion.
23.2.4
The INTCTL register is a word-wide read/write register. It
contains the interrupt enable bits for all 16 interrupt sources
of the VTU. Each interrupt enable bit corresponds to an in-
terrupt pending bit located in the Interrupt Pending Register
(INTPND). All INTCTL register bits are solely under soft-
ware control. The register is clear after reset.
IxAEN
IxBEN
P6POL
P8POL
I2DEN I2CEN I2BEN I2AEN I1DEN I1CEN I1BEN I1AEN
I4DEN I4CEN I4BEN I4AEN I3DEN I3CEN I3BEN I3AEN
15
15
7
7
I/O Control Register 2 (IO2CTL)
Interrupt Control Register (INTCTL)
14
6
14
6
The Timer x Interrupt A Enable bit controls in-
terrupt requests triggered on the correspond-
ing IxAPD bit being set. The associated
IxAPD bit will be updated regardless of the
value of the IxAEN bit.
0 – Disable system interrupt request for the
1 – Enable system interrupt request for the Ix-
The Timer x Interrupt B Enable bit controls in-
terrupt requests triggered on the correspond-
ing IxBPD bit being set. The associated
IxBPD bit will be updated regardless of the
value of the IxBEN bit.
0 – Disable system interrupt request for the
1 – Enable system interrupt request for the Ix-
C6EDG
C8EDG
13
IxAPD pending bit.
APD pending bit.
IxBPD pending bit.
BPD pending bit.
5
12
12
4
4
P5POL
P7POL
11
11
3
3
10
2
10
2
C5EDG
C7EDG
1
9
0
8
0
8