cp3cn17 National Semiconductor Corporation, cp3cn17 Datasheet - Page 217

• Manufacturer Part Number: cp3cn17
• Description: Reprogrammable Connectivity Processor With Can Interface
• Manufacturer: National Semiconductor Corporation

28.0 Revision History
10/14/02
10/16/02
11/11/02
11/21/02
11/14/03
1/13/03
5/20/03
2/28/04
3/16/04
6/23/04
7/3/04
Date
Original release of full CP3CN17 datasheet.
Corrections to flash memory programming
sequence and MFT block diagrams.
Numerous minor corrections. Added more
description to AAI section. Added external
reset circuit. Fixed problems with figures.
Converted to new format.
Removed erroneous warning to always
write the IOCFG register with bit 1 set.
Alternate clock source for Advanced Audio
Interface changed to Aux1 clock. Changed
warning about clock glitches to say
Microwire interface must be disabled when
modifying bits in MWCTL1 register.
Changed bit settings which occur in step 2
of the sequence of ACCESS.bus slave
mode address match or global match. Timer
Mode Control Register bit 7 is the TEN bit (a
bit description has been added). Polarity of
all of the bits in the INTCTL register has
been inverted.
Updated DC specifications. Fixed errors in
Microwire bit and pin names. Changed
UART pin names to TXD and RXD. Added
Section 11.6 “Auxiliary Clocks”. Changed
diagram of I/O Port Pin Logic (Section 14).
Defined valid range of SCDV field in
Microwire/SPI module. Noted default
PRSSC register value generates a Slow
Clock frequency slightly higher than 32768
Hz. Clarified usage of CVSTAT register bits
and fields in CVSD/PCM module. Added
usage hint for avoiding ACCESS.bus
module bus error. Added usage hint for
avoiding CAN unexpected loopback
condition.
Added entry for CTIM register in CAN
section register list. Changed CVSD
Conversion section. Changed definition of
the RESOLUTION field of the CVSD
Control register (CVCTRL). Changed DC
specification for Vxl2.
Updated DC specifications Iccid and Iccq.
Moved revision history in front of physical
dimensions. Changed back page
disclaimers. Changed absolute maximum
supply voltage to 3.6V. Changed processor
selection guide table.
Changed footnote b in DC specs. Changed
product selection guide table.
Major Changes From Previous Version
Table 79 Revision History
217
7/16/04
8/24/04
9/7/04
4/4/05
Date
Table 79 Revision History (Continued)
Changed product selection guide table.
Added AC timing specifications for GPIO
and UART.
In Section 17.2, added sentence that an
external frame sync must be used in
asynchronous mode. In Section 12, in
several places noted that Idle and Halt
modes may only be entered from Active
mode, and the DHC and DMC bits must be
set when entering Idle and Halt modes.
Added usage hints Section 16.8. Removed
Section 20.4.1.
Added new reset circuits. Added note about
fluctuations in response due to SDI activity.
New back page.
Major Changes From Previous Version
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