tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 74

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

5.9
Port P8 (P87 to P80)
5.9
Table 5-6
Note 1: i = 7 to 2
Note 2: j = 1, 0
Note 3: OFDRST shows a reset signal of oscillation frequency detection.
output control register (P8CR). When reset, the P8CR register is initialized to 0, with the P8 port set for input mode.
Also, the output latch (P8DR) is initialized to 0 when reset.
is used to select open-drain or tri-state mode for the port. When reset, the P8ODE register is initialized to 0, with tri-
state mode selected for the port.
the oscillation frequency detection reset and Port P8 becomes high impedance.
Port P8 (P87 to P80)
Port P8 is an 8-bit input/output port. This port is switched between input and output modes using the P8 port input/
The P8 port contains bit wise programmable open-drain control. The P8 port open-drain control register (P8ODE)
If high frequency oscillation stops or becomes abnormal in NORMAL/IDLE mode, the TMP88FW45AFG generates
P8ODE
0
0
0
0
1
1
1
1
Control output
P8CR
Control input
Data output
0
0
1
1
0
0
1
1
Data output
Data input
Data input
OFDRST
OFDRST
P8ODEj
P8ODEi
OUTEN
OUTEN
P8CRj
P8CRi
STOP
STOP
P8DR
0
1
0
1
0
1
0
1
Output latch
Output latch
D
D
Data input (by reading instruction)
Q
Q
Figure 5-10 Port P8
Input Data from port (Low)
Input Data from port (Low)
"0" (output latch data)
"1" (output latch data)
Input Data from port
Input Data from port
Input Data from port
Input Data from port
Page 60
Input Data from port (Low)
Input Data from port (Low)
"0" (output latch data)
"1" (output latch data)
Input Data from port
Input Data from port
Input Data from port
Input Data from port
Control input
P8j
P8i
TMP88FW45AFG
Output data
Hi-Z
Hi-Z
Hi-Z
Hi-Z
"0"
"1"
"0"
"0"