tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 125

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Example :Inputting 50 Hz pulse to TC3, and generating interrupts every 0.5 s
11.3.2
up-counter is cleared. After being cleared, the up-counter restarts counting at each rising edge of the input pulse
to the TC3 pin. Since a match is detected at the falling edge of the input pulse to TC3 pin, an INTTC3 interrupt
request is generated at the falling edge immediately after the up-counter reaches the value set in TC3DRA.
is required for high-going and low-going pulses.
count value during a timer operation can be checked by the read instruction to TC3DRB.
TC3 pin input
Counter
TC3DRA
INTTC3 interrupt
In the event counter mode, the up-counter counts up at the rising edge of the input pulse to the TC3 pin.
When a match between the up-counter and TC3DRA value is detected, an INTTC3 interrupt is generated and
The maximum applied frequencies are shown in Table 11-2. The pulse width larger than one machine cycle
Setting TC3CR<ACAP> to 1 captures the up-counter value into TC3DRB with the auto-capture function. The
Event Counter Mode
Note:00H which is stored in the up-counter immediately after detection of a match is not captured into TC3DRB.
(Figure 11-2)
Table 11-2 Maximum Frequencies Applied to TC3
LD
LD
LD
High-going
Low-going
Timer start
Figure 11-4 Event Counter Mode Timing Chart
0
(TC3CR), 00001110B
(TC3DRA), 19H
(TC3CR), 00011110B
1
2
n
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3
NORMAL, IDLE mode
Minimum Pulse Width
: Sets the clock mode
: 0.5 s ÷ 1/50 = 25 = 19H
: Starts TC3.
2
2
2
2
/fc
/fc
Match detect
n
0
Counter clear
1
2
TMP88FW45AFG
3