tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 49

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.5
Source
INT0
INT1
INT2
INT4
INT5
External Interrupt Control Register
(Pulse inputs of less than a certain time are eliminated as noise).
interrupt input pin or an input/output port, and is configured as an input port during reset.
control register (EINTCR).
EINTCR
(0037H)
External Interrupts
The TMP88FW45AFG has 5 external interrupt inputs. These inputs are equipped with digital noise reject circuits
Edge selection is also possible with INT1,INT2 and INT4. The INT0/P10 pin can be configured as either an external
Edge selection, and noise reject control and INT0/P10 pin function selection are performed by the external interrupt
Note 1: In NORMAL or IDLE mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "signal
Note 2: When EINTCR<INT0EN> = "0", IL3 is not set even if a falling edge is detected on the INT0 pin input.
Note 3: When a pin with more than one function is used as an output and a change occurs in data or input/output status, an
Note 1: fc: High-frequency clock [Hz], *: Don’t care
Note 2: When the external interrupt control register (EINTCR) is overwritten, the noise canceller may not operate normally. It is
Note 3: The maximum time from modifying EINTCR<INT1NC> until a noise reject time is changed is 2
Note 4: In case RESET pin is released while the state of INT4 pin keeps "H" level, the external interrupt 4 request is not generated
INT1NC
INT0
INT1
INT2
INT4
INT5
establishment time" from the input signal's edge to set the interrupt latch.
(1) INT1 pin 49/fc [s] ( at EINTCR<INT1NC> = "1") , 193/fc [s] ( at EINTCR<INT1NC> = "0")
(2) INT2 , 4 pins 25/fc [s]
interrupt request signal is generated in a pseudo manner. In this case, it is necessary to perform appropriate processing
such as disabling the interrupt enable flag.
recommended that external interrupts are disabled using the interrupt enable register (EIR).
even if the INT4 edge select(EINTCR<INT4ES>) is specified as "H" level. The rising edge is needed after RESET pin is
released.
Pin
7
INT1NC
INT0EN
INT4 ES
INT2 ES
INT1 ES
INT0EN
P20/STOP
6
P12/TC1
P22/TC4
Sub-Pin
P10
P11
Noise reject time select
P10/INT0 pin configuration
INT4 edge select
INT2 edge select
INT1 edge select
5
IMF + EF3 + INT0EN=1
IMF + EF5 = 1
IMF + EF29 = 1
IMF + EF31 = 1
IMF + EF15 = 1
INT4ES
Enable Conditions
4
3
-
Page 35
0: Pulses of less than 63/fc [s] are eliminated as noise
1: Pulses of less than 15/fc [s] are eliminated as noise
0: P10 input/output port
1: INT0 pin (Port P10 should be set to an input mode)
00: Rising edge
01: Falling edge
10: Rising edge and Falling edge
11: H level
0: Rising edge
1: Falling edge
Falling edge
Falling edge
or
Rising edge
Falling edge
INT2ES
Release Edge (level)
2
INT1ES
1
Pulses of less than 2/fc [s] are eliminated as
noise. Pulses of 6/fc [s] or more are considered
to be signals. (at CGCR<DV1CK>=0).
Pulses of less than 15/fc or 63/fc [s] are elimina-
ted as noise. Pulses of 48/fc or 192/fc [s] or more
are considered to be signals.
(at CGCR<DV1CK>=0).
Pulses of less than 7/fc [s] are eliminated as
noise. Pulses of 24/fc [s] or more are considered
to be signals.(at CGCR<DV1CK>=0).
Pulses of less than 2/fc [s] are eliminated as
noise. Pulses of 6/fc [s] or more are considered
to be signals.
0
(Initial value: 0000 *00*)
Digital Noise Reject
TMP88FW45AFG
6
/fc.
R/W
R/W
R/W
R/W