tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 220

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

17.6
Transfer Mode
17.6.2
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
INTSIO interrupt
SCK pin
(Input)
SO pin
DBR
are then transferred to the shift register via the SI pin in synchronous with the serial clock. When one word of
data has been received, it is transferred from the shift register to the data buffer register (DBR). When the number
of words specified with the SIOCR2<BUF> has been received, an INTSIO (Buffer full) interrupt is generated to
request that these data be read out. The data are then read from the data buffer registers by the interrupt service
program.
data are received, the serial clock will stop and an automatic-wait will be initiated until the data are read. A wait
will not be initiated if even one data word has been read.
previous data are read before the next data are transferred to the data buffer register. If the previous data have
not been read, the next data will not be transferred to the data buffer register and the receiving of any more data
will be canceled. When an external clock is used, the maximum transfer speed is determined by the delay between
the time when the interrupt request is generated and when the data received have been read.
Figure 17-8 Transfer Mode (Example: 8bit, 1word transfer, External clock)
After setting the control registers to the receive mode, set SIOCR1<SIOS> to “1” to enable receiving. The data
When the internal clock is used, and the previous data are not read from the data buffer register before the next
When an external clock is used, the shift operation is synchronized with the external clock; therefore, the
4-bit and 8-bit receive modes
Note:Waits are also canceled by reading a DBR not being used as a received data buffer register is read;
SCK pin
SIOSR<SIOF>
SO pin
therefore, during SIO do not use such DBR for other applications.
Figure 17-9 Transmitted Data Hold Time at End of Transfer
Write
(a)
a
Write
a
(b)
0
b
a
1
a
2
a
3
a
4
MSB of last word
a
t
SODH
Page 206
5
= min 3.5/fc [s] (In the NORMAL, IDLE modes)
a
6
a
7
b
0
b
1
b
2
Clear SIOS
b
3
b
4
b
5
TMP88FW45AFG
b
6
b
7