tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 44

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.3
Interrupt Sequence
3.3
3.3.1
Interrupt
request
Interrupt
latch (IL)
IMF
Execute
instruction
PC
SP
Note 1: a: Return address, b: Entry address, c: Address which RETI instruction is stored
Note 2: On condition that interrupt is enabled, it takes 62/fc [s] at maximum (If the interrupt latch is set at the first machine
“0” by resetting or an instruction. Interrupt acceptance sequence requires 12 machine cycles (2.4 μs @20 MHz) after
the completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return
instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing
chart of interrupt acceptance processing.
An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to
Interrupt Sequence
Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction
service program
Interrupt acceptance processing is packaged as follows.
cycle on 15 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set.
1-machine cycle
Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt
Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved.
a. The interrupt master enable flag (IMF) is cleared to “0” in order to disable the acceptance of any
b. The interrupt latch (IL) for the interrupt source accepted is cleared to “0”.
c. The contents of the program counter (PC) and the program status word, including the interrupt master
d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector
e. Read the RBS control code from the vector table, add its MSB(4bit) to the register bank selector (RBS).
f.
g. The instruction stored at the entry address of the interrupt service program is executed.
a-1
instruction
Execute
following interrupt.
enable flag (IMF), are saved (Pushed) on the stack in sequence of PSWH, PSWL, PCE, PCH, PCL.
Meanwhile, the stack pointer (SP) is decremented by 5.
table, is transferred to the program counter.
Count up the interrupt nesting counter.
a
a+1
n
Interrupt acceptance
a
n-1
n-2
n-3 n-4
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b b+1 b+2
instruction
Execute
n-5
b+3
c+1
Interrupt service task
n-4
Execute RETI instruction
n-3
c+2
n-2 n-1
TMP88FW45AFG
a
a+1 a+2
n