tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 246
tmp88fw45afg
Manufacturer Part Number
tmp88fw45afg
Description
8 Bit Microcontroller Tlcs-870/x Series
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP88FW45AFG.pdf
(294 pages)
- Current page: 246 of 294
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20.4
Access to the Flash Memory Area
Example :After chip erasure, the program in the RAM area writes data 3FH to address F000H.
; #### Flash Memory Chip erase Process ####
sLOOP1:
; #### Flash Memory Write Process ####
sLOOP2:
sLOOP3:
Note 2: Since the watchdog timer is disabled by the BOOTROM in the RAM loader mode, it is not required to
disable the watchdog timer by the RAM loader program.
DI
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
CMP
JR
LD
LD
LD
LD
LD
CMP
JR
LD
JP
(FLSCR),0011_1000B
IX,04555H
IY,04AAAH
HL,0F000H
(IX),0AAH
(IY),55H
(IX),80H
(IX),0AAH
(IY),55H
(IX),10H
A,(IX)
A,(IX)
NZ,sLOOP1
(IX),0AAH
(IY),55H
(IX),0A0H
(HL),3FH
A,(HL)
A,(HL)
NZ,sLOOP2
(FLSCR),1100_1000B
sLOOP3
Page 232
: Disable interrupts (IMF← "0")
: Enable command sequence execution.
: 1st bus write cycle
: 2nd bus write cycle
: 3rd bus write cycle
: 4th bus write cycle
: 5th bus write cycle
: 6th bus write cycle
: Loop until the same value is read.
: 1st bus write cycle
: 2nd bus write cycle
: 3rd bus write cycle
: 4th bus write cycle, (F000H) = 3FH
: Loop until the same value is read.
: Disable command sequence execution.
TMP88FW45AFG
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