tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 28

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.1
Functions of the CPU Core
2.1.4.3
system clock. The System Control Registers (SYSCR1, SYSCR2) are used to control operation modes of this
circuit. Figure 2-6 shows an operation mode transition diagram, followed by description of the System Control
Registers.
Table 2-1 Single Clock Mode
(1)
The Standby Control Circuit starts/stops the high-frequency clock oscillator circuit and selects the main
Standby Control Circuit
Single
Clock
from the high-frequency clock, the machine cycle time in single clock mode is 4/fc [s].
Operation Mode
mode
IDLE
Only the high-frequency clock oscillator circuit is used. Because the main system clock is generated
Single clock mode
1. NORMAL mode
2. IDLE mode
3. STOP mode
RESET
NORMAL
IDLE
STOP
quency clock. The TMP88FW45AFG enters this NORMAL mode after reset.
are operated with the high-frequency clock. IDLE mode is entered into by using System Control
Register 2. The device is placed out of this mode and back into NORMAL mode by an interrupt
from the peripheral hardware or an external interrupt. When IMF (interrupt master enable flag)
= 1 (interrupt enabled), the device returns to normal operation after the interrupt has been
serviced. When IMF = 0 (interrupt disabled), the device restarts execution beginning with the
instruction next to one that placed it in IDLE mode.
state immediately before being stopped, with a minimal amount of power consumed.
input (level or edge selectable). After an elapse of the warm-up time, the device restarts exe-
cution beginning with the instruction next to one that placed it in STOP mode.
Figure 2-6 Operation Mode Transition Diagram
In this mode, the CPU core and peripheral hardware units are operated with the high-fre-
In this mode, the CPU and watchdog timer are turned off while the peripheral hardware units
The entire system operation including the oscillator circuit is halted, retaining the internal
STOP mode is entered into by using System Control Register 1, and is exited by STOP pin
Instruction
Interrupt
Frequency
Oscillate
High
Stop
Oscillator Circuit
Frequency
Low
-
NORMAL
Page 14
RESET
mode
Reset deasserted
CPU Core
Operate
Reset
Stop
Input for releasing mode
Instruction
Peripheral
Operate
Circuit
Reset
Stop
Machine Cycle
STOP
mode
4/fc [s]
Time
-
TMP88FW45AFG