tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 155

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

PDCRC
PDCRB
PDCRA
SDREG
14.3.2
2 to 0
3 to 0
6 to 0
5, 4
7, 6
5, 4
3
7
6
5
4
3
2
1
0
Position Detection Circuit Register Functions
PDNUM
PDCMP
SWSTP
SWSTT
PDCEN
SDREG
PDTCT
SPLMD
SPTM3
SPLCK
STTM2
EMEM
SMON
RCEN
DTMD
・ A sampling delay is provided for use in modes where sampling is made while PWM is on or the lower
・ When detecting position while PWM is on or the lower phases are conducting current, a method can
phases are conducting current. It helps to prevent erroneous detection due to noise that occurs imme-
diately after the transistor turns on, by starting sampling a set time after the PWM signal turned on.
be selected whether to recount occurrences of matched position detection after being compared for each
PWM signal on (logical sum of three-phase PWM signals) (e.g., starting from 0 in each PWM cycle)
or counting occurrences of matching continuously ( PDCRB<SPLMD> is used to enable/disable re-
counting occurrences of matching while PWM is on).
Hold result of position detec-
tion at PWM edge
(Detect position detected po-
sition)
Monitor sampling status
Hold position signal input sta-
tus
Sampling period
Sampling mode
Sampling count
Stop sampling in software
Start sampling in software
Stop sampling using Timer 3
Start sampling using Timer 2
Number of position signal in-
put pins
Recount occurrences of
matching when PWM is on
Position detection mode
Position detection function
Sampling delay
These bits hold the comparison result of position detection at falling or rising edge of PWM
pulse. Bits 5 and 4 are set to 1 when position is detected at the falling or the rising edge,
respectively. They show whether position is detected in the current PWM pulse, during
PWM off, or in the immediately preceding PWM pulse.
When read, this bit shows the sampling status.
This bit holds the status of the position signal input at the time position detection started in
unmatch mode.
Select fc/2
Select one of three modes: sampling only when PWM signal is active (when PWM is on),
sampling regularly, or sampling when the lower side (X, Y, Z) phases are conducting cur-
rent.
In ordinary mode, when the port status and the set expected value match and continuously
match as many times as the sampling counts set, a position detection signal is output and
an interrupt is generated. In unmatch detection mode, when the said status and value do
not match and continuously unmatch as many times as the sampling counts set, a position
detection signal is output and an interrupt is generated.
Sampling can be stopped in software by setting this bit to 1 (e.g., by writing to this register).
Sampling is performed before stopping and when position detection results match, a po-
sition detection interrupt is generated, with sampling thereby stopped.
Sampling can be started by setting this bit to 1 (e.g., by writing to this register).
Sampling can be stopped by a trigger from Timer 3 by setting this bit to 1.
Sampling is performed before stopping and when position detection results match, a po-
sition detection interrupt is generated, with sampling thereby stopped.
Sampling can be started by a trigger from Timer 3 by setting this bit to 1.
Select whether to use three pins (PDU/PDV/PDW) or one pin (PDU only) for position signal
input. When one pin is selected, the expected values of PDV and PDW are ignored. When
performing position detection with two pins or a pin other than PDU, position signal input
can be masked as 0 by setting unused pin(s) for output.
When performing sampling while PWM is on, occurrences of matching are recounted each
time PWM signal turns on by setting this bit to 1 (when recounting occurrences of matching,
the count is reset each time PWM turns off). When this bit is set to 0, occurrences of
matching are counted continuously regardless PWM interval.
Setting this bit to 0 selects ordinary mode where position is detected when the expected
value set in the register and the port input unmatch and then match.
Setting this bit to 1 selects unmatch detection mode where position is detected at the time
the port status changes to another one from the status in which it was when sampling
started.
The position detection function is activated by setting this bit to 1.
Set a time for which to stop sampling in order to prevent erroneous detection due to noise
that occurs immediately after PWM output turns on (immediately after the transistor turns
on). (Figure 14-5)
Page 141
2
, fc/2
3
, fc/2
4
, or fc/2
5
for the position detection sampling period.
TMP88FW45AFG