tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 64

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

5.4
Port P3 (P37 to P30)
5.4
Table 5-3
Note 1: i = 7 to 0
Note 2: OFDRST shows a reset signal of oscillation frequency detection.
output Control Register (P3CR). When reset, the P3CR Register is initialized to 0, with the P3 port set for input mode.
Also, the Output Latch (P3DR) is initialized to 0 when reset.
is used to select open-drain or tri-state mode for the port. When reset, the P3ODE Register is initialized to 0, with tri-
state mode selected for the port.
the oscillation frequency detection reset and Port P3 becomes high impedance.
Port P3 (P37 to P30)
Port P3 is an 8-bit input/output port. This port is switched between input and output modes using the P3 port Input/
The P3 port contains bit wise programmable open-drain control. The P3 Port Open-drain Control Register (P3ODE)
If high frequency oscillation stops or becomes abnormal in NORMAL/IDLE mode, the TMP88FW45AFG generates
P3ODE
0
0
0
0
1
1
1
1
P3CR
Control output
Control input
0
0
1
1
0
0
1
1
Data output
Data input
OFDRST
P3ODEi
OUTEN
P3CRi
STOP
P3DR
0
1
0
1
0
1
0
1
Output latch
D
Data input (by reading instruction)
Q
Input Data from port (Low)
Input Data from port (Low)
Figure 5-5 Port P3
"0" (output latch data)
"1" (output latch data)
Input Data from port
Input Data from port
Input Data from port
Input Data from port
Page 50
Input Data from port (Low)
Input Data from port (Low)
"0" (output latch data)
"1" (output latch data)
Input Data from port
Input Data from port
Input Data from port
Input Data from port
Control input
P3i
TMP88FW45AFG
Output data
Hi-Z
Hi-Z
Hi-Z
Hi-Z
"0"
"1"
"0"
"0"