tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 41

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Example :Enables interrupts individually and sets IMF
3.2
3.2.1
3.2.2
maskable interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt).
Pseudo non-maskable interrupt is accepted regardless of the contents of the EIR.
registers are located on address 003AH, 003BH, 002CH, 002DH and 002AH in SFR area, and they can be read and
written by an instructions (Including read-modify-write instructions such as bit manipulation or operation instructions).
Interrupt enable register (EIR)
The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the pseudo non-
The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These
IMF = “0”, all maskable interrupts are not accepted regardless of the status on each individual interrupt enable
flag (EF). By setting IMF to “1”, the interrupt becomes acceptable if the individuals are enabled.
interrupts which follow are disabled temporarily. IMF flag is set to "1" by the maskable interrupt return instruction
[RETI] after executing the interrupt service program routine, and MCU can accept the interrupt again. The latest
interrupt request is generated already, it is available immediately after the [RETI] instruction is executed.
IMF flag is set to "1" only when it performs the pseudo non-maskable interrupt service routine on the interrupt
acceptable status (IMF=1). However, IMF is set to "0" in the pseudo non-maskable interrupt service routine, it
maintains its status (IMF="0").
The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initialized
to “0”.
bit of an individual interrupt enable flag to “1” enables acceptance of its interrupt, and setting the bit to “0”
disables acceptance. During reset, all the individual interrupt enable flags (EF39 to EF3) are initialized to “0”
and all maskable interrupts are not accepted until they are set to “1”.
Interrupt master enable flag (IMF)
Individual interrupt enable flags (EF39 to EF3)
The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt. While
When an interrupt is accepted, IMF is cleared to “0” after the latest status on IMF is stacked. Thus the maskable
On the pseudo non-maskable interrupt, the non-maskable return instruction [RETN] is adopted. In this case,
The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction.
Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding
Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to
clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating
on the EF or IL (Enable interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute
normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine,
manipulating EF or IL should be executed before setting IMF="1".
DI
SET
CLR
CLR
CLR
:
EI
(EIRL), .5
(EIRL), .6
(EIRH), .4
(EIRD), .0
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; IMF ← 0
; EF5 ← 1
; EF6 ← 0
; EF12 ← 0
; EF24 ← 0
; IMF ← 1
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