stlc5465 STMicroelectronics, stlc5465 Datasheet - Page 88

• Manufacturer Part Number: stlc5465
• Description: Multi Hdlc With Switching Matrix Associated
• Manufacturer: STMicroelectronics

STLC5465B
VIII - INTERNAL REGISTERS (continued)
NOBT : NUMBER OF BYTE which has been transmitted.
L
ABT
TO
VIII.24 - Transmit Monitor Data Register - TMDR (2E)H
M08/01 : First Monitor Byte to transmit. M08 bit is transmitted first.
M18/11 : Second Monitor Byte to transmit if NOB = 0 (bit of TMAR). M18 bit is transmitted first.
VIII.25 - Transmit Monitor Interrupt Register - TMIR (30)H
When the microprocessor read this register, this register is reset (0000)H.
MIxy
VIII.26 - Memory Interface Configuration Register - MICR (32)H
REF
R,S,T : These three bits define the external RAM circuit organization (1word=2bytes)
88/101
bit15
bit15
MI71
bit15
M18
P41
MI61
M17
: Last byte ; this L bit is the L bit which has been written by the microprocessor.
: ABORT
: Time Out one millisecond
: Transmit Monitor Channel x Interrupt, Multiplex y with :
P40
: MEMORY REFRESH
NOBT = 1, the first byte is transmitting.
NOB T = 0, the second byte is transmitting, the first byte has been transmitted.
ABT=1, the remote receiver has aborted the current message.
TO = 1, the remote receiver has not acknowledged the byte which has been transmitted one
millisecond ago.
0
y = 0, GCI CHANNEL belongs to the multiplex TDM4 and y = 1 to TDM5.
MIxy = 1 when :
- a word has been transmitted and pre-acknowledged by the Transmit Monitor Channel xy (In
- the message has been aborted by the remote receive Monitor Channel or
- the Timer has reached one millisecond (in accordance with TIV bit of TMAR) by IM3 bit of IMR.
When MIxy goes to "1", the Interrupt MTX bit of IR is generated. Interrupt MTX can be masked.
REF = 1, DRAM REFRESH is validated,
REF = 0, DRAM REFRESH is not validated.
The cycle duration is always 15.625ms (512 periods of the clock applied on XTAL1 pin).
The cycle duration is always 15.625ms (512 periods of the clock applied on XTAL1 Pin).
T
0
0
0
0
1
1
this case the Transmit Monitor Data Register (TMDR) is available to transmit a new word) or
MI51
x
M16
P31
S
0
0
1
1
0
0
7, 1 of 8 GCI CHANNELS belonging to the same multiplex TDM4 or TDM5
R
0
1
0
1
0
1
MI41
M15
P30
128K x 8 SRAM circuit (up to 512K words)
512K x 8 SRAM circuit (up to 512K words)
256K x 16 DRAM circuit (up to 1M word)
1M x 4 (or 16) bits DRAM circuit (up to 4M words)
4M x 4 (or 16) bits DRAM circuit (up to 8M words)
101 to 111 not used (this writting is forbidden)
TDM5
MI31
M14
P21
MI21
M13
P20
MI11
M12
P11
After reset (FFFF)
After reset (E4F0)
After reset (0000)
MI01
M11
P10
bit8
bit8
bit8
MI70
M08
bit7
bit7
bit7
Z
H
H
H
MI60
M07
W
MI50
M06
V
MI40
M05
U
TDM4
MI30
M04
T
MI20
1024 cycles / 16ms
2048 cycles / 32ms
M03
512 cycles / 8ms
S
If refresh
MI10
M02
R
MI00
M01
REF
bit 0
bit 0
bit 0