stlc5465 STMicroelectronics, stlc5465 Datasheet - Page 80

• Manufacturer Part Number: stlc5465
• Description: Multi Hdlc With Switching Matrix Associated
• Manufacturer: STMicroelectronics

STLC5465B
VIII - INTERNAL REGISTERS (continued)
HDI
N.B.
VIII.12 - Time Slot Assigner Data Register - TADR (16)H
CH0/4 : CHANNEL0/4
V1/8
V9
V10
V11
80/101
bit15
V11
: HDLC INIT
V10
: VALIDATION
: VALIDATION SUBCHANNEL
: DIRECT MHDLC ACCESS
: VALIDATION of CB pin
working. The automate is stopped when the microprocessor writes TAAR Register with HDI = 0.
After software reset (bit 2 of IDCR Register) or pin reset the automate above-mentioned is
HDI = 1, TSA Memory, Tx HDLC, Tx DMA, Rx HDLC, Rx DMA and GCI controllers are reset
within 250ms. An automate writes data from Time slot Assigner Data Register (TADR) (except
CH0/4 bits) into each TSA Memory location. If the microprocessor reads Time slot Assigner
Memory after HDLC INIT, CH0/4 bits of Time slot Assigner Data Register are identical to TS0/4
bits of Time slot Assigner Address Register.
HDI = 0, Normal state.
These five bits define one of 32 channels associated to TIME SLOT defined by the previous
Register (TAAR).
The logical channel CHx is constituted by each subchannel 1 to 8 and validated by V1/8 bit at
1 respectively.
V1 to V8 at 0: the subchannels are ignored
V1 at 1: the first bit of the current time slot is taken into account in reception the first bit received
and in transmission the first bit transmitted.
V8 at 1: the last bit of the current time slot is taken into account in reception the last bit received
and in transmission the last bit transmitted in transmission.
V 9 = 1, each V1/8 bit is taken into account once every 250ms.
In transmit direction, data is transmitted consecutively during the time slot of the current frame
and during the same time slot of the next frame.Id est.: the same data is transmitted in two
consecutive frames.
In receive direction, HDLC controller fetches data during the time slot of the current frame and
ignores data during the same time slot of the next frame.
V 9 = 0, each V1/8 bit is taken into account once every 125ms.
If V10 = 1, the Rx HDLC Controller receives data issued from DIN8 input during the current time
slot (bits validated by V1/8) and DOUT6 output transmits data issued from the Tx HDLC
Controller.
If V10 = 0, the Rx HDLC Controller receives data issued from the matrix output 7 during the
current time slot ; DOUT6 output delivers data issued from the matrix output 6 during the same
current time slot.
N.B : If D7 = 1, (see "General Configuration Register GCR (02)H") the Tx HDLC controller is
connected to matrix input 7 continuously so the HDLC frames can be sent to any DOUT (i.e.
DOUT0 to DOUT7).
This bit is not taken into account if CSMA = 1 (HDLC Transmit Command Register).
if CSMA = 0 :
V11 = 1, Contention Bus pin is validated and Echo pin (which is an input) is not taken into
account.
V11 = 0, Contention Bus pin is high impedance during the current time slot (This pin is an open
drain output).
V9
V8
V7
V6
V5
After reset (0000)
bit8
V4
bit7
V3
H
V2
V1
CH4
CH3
CH2
CH1
CH0
bit 0