stlc5465 STMicroelectronics, stlc5465 Datasheet - Page 25

• Manufacturer Part Number: stlc5465
• Description: Multi Hdlc With Switching Matrix Associated
• Manufacturer: STMicroelectronics

III - FUNCTIONAL DESCRIPTION (continued)
III.2 - HDLC Controller
III.2.1 - Function Description
The internal HDLC controller can run up to 32
channels in a conventional HDLC mode or in a
transparent (non-HDLC) mode (configurable per
channel).
Each channel bit rate is programmable from 4kbit/s
to 64kbit/s. All the configurations are also possible
from 32 channels (from 4 to 64 kbit/s) to one
channel at 2 Mbit/s.
In reception, the HDLC time slots can directly come
from the input TDM DIN8 (direct HDLC Input) or
from any other TDM input after switching towards
the output 7 of the matrix (configurable per time
slot).
In transmission, the HDLC frames are sent on the
output DOUT6 and on the output CB (with or with-
out contention mechanism), or are switched to-
wards the other TDM output via the input 7 of the
matrix (see Figure 11).
III.2.1.1 - Format of the HDLC Frame
The format of an HDLC frame is the same in receive
and transmit direction and shown here after.
Figure 11 : HDLC and DMA Controller Block Diagram
III.2.1.2 - Composition of an HDLC Frame
- Opening Flag
- One or two bytes for address recognition (recep-
- Data bytes with bit stuffing
- Frame Check Sequence: CRC with polynomial
- Closing Flag.
tion) and insertion (transmission)
G(x) = x
16
Command Field (second byte)
+x
Address Field (second byte)
Command Field (first byte)
Address Field (first byte)
12
+x
FCS (second byte)
Data (first byte)
Data (last byte)
FCS (first byte)
Data (optional)
5
Opening Flag
Closing Flag
+1
STLC5465B
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