stlc5465 STMicroelectronics, stlc5465 Datasheet - Page 71

• Manufacturer Part Number: stlc5465
• Description: Multi Hdlc With Switching Matrix Associated
• Manufacturer: STMicroelectronics

VIII - INTERNAL REGISTERS (continued)
LP (i)
N.B. If DIN4 and DIN5 are GCI Multiplexes : then ST(4)1 = ST(4)0 = 0 and ST(5)1 = ST(5)0 = 0 normally.
VIII.5 - Output Multiplex Configuration Register 0 - OMCR0 (08)H
See definition in next Paragraph.
VIII.6 - Output Multiplex Configuration Register 1 - OMCR1 (0A)H
ST(i)0 : STEP0 for each Output Multiplex i(0
ST(i)1 : STEP1 for each Output Multiplex i(0
DEL(i); : DELAYED Multiplex i(0
OMV (i): Output Multiplex Validated 0/7
N.B. If DIN4 and DIN5 are GCI Multiplexes : then ST(4)1 = ST(4)0 = 0 and ST(5)1 = ST(5)0 = 0 normally.
VIII.7 - Switching Matrix Configuration Register - SMCR (0C)H
IMTD
OMV3 DEL3 ST(3)1 ST(3)0 OMV2 DEL2 ST(2)1 ST(2)0 OMV1 DEL1 ST(1)1 ST(1)0 OMV0 DEL0 ST(0)1 ST(0)0
OMV7 DEL7 ST(7)1 ST(7)0 OMV6 DEL6 ST(6)1 ST(6)0 OMV5 DEL5 ST(5)1 ST(5)0 OMV4 DEL4 ST(4)1 ST(4)0
bit15
bit15
bit15
SW1
SW0
: LOOPBACK 0/7
: Increased Minimum Throughput Delay
LPi = 1, Output Multiplex i is put instead of Input Multiplex i (0 i 7). LOOPBACK is transparent
or not in accordance with OMVi (bit of Output Multiplex Configuration Register).
LPi = 0, Normal case, Input Multiplex i(0
When IMTD = 0 (bit of SMCR), DEL = 0 is not taken into account by the circuit.
1/2 bit time 244ns if TDM at 2048 kHz,
1/2 bit time 122ns if TDM at 4096 kHz.
OMVi =1, condition to have DOUTi pin active (0
OMVi =0, DOUTi pin is High Impedance continuously (0
When SI = 0 (bit of CMDR, variable delay mode) :
IMTD = 1, the minimum delay through the matrix memory is three time slots whatever the selected
TDM output.
IMTD = 0, the minimum delay through the matrix memory is two time slots whatever the selected
TDM output.
When IMTD = 0, the input TDMs cannot be delayed versus the frame synchronization (Use
of IMCR is limited) and the output TDMs cannot be advanced versus the frame
synchronization.(Use of OMCR is limited).
DEL (i) ST (i) 1 ST (i) 0
X
1
1
1
0
0
0
M1
M0
0
0
1
1
0
1
1
DR64 DR44 DR24 DR04 AISD
0
1
0
1
1
0
1
Each bit is transmitted on the rising edge of the double clock without delay.
Bit 0 is defined by Frame synchronization Signal.
Each bit is transmitted with 1/2 bit-time delay.
Each bit is transmitted with 1 bit-time delay.
Each bit is transmitted with 2 bit-time delay.
Each bit is transmitted with 1/2 bit-time advance.
Each bit is transmitted with 1 bit-time advance
Each bit is transmitted with 2 bit-time advance.
i
7).
After reset (0000)
After reset (0000)
After reset (0000)
STEP for each Output Multiplex 0/7 delayed or not
bit8
bit8
bit8
i
i
7), delayed or not.
7), delayed or not.
i
bit7
bit7
bit7
7) is taken into account.
H
H
H
i
ME
7).
SGC
i
7).
SAV
SGV
TS1
STLC5465B
TS0
71/101
IMTD
bit 0
bit 0
bit 0