stlc5465 STMicroelectronics, stlc5465 Datasheet - Page 50
stlc5465
Manufacturer Part Number
stlc5465
Description
Multi Hdlc With Switching Matrix Associated
Manufacturer
STMicroelectronics
Datasheet
1.STLC5465.pdf
(101 pages)
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VI - MEMORY TIMING (continued)
Figure 39 : Dynamic Memory Write Signals from the Multi-HDLC
Note : Total Cycle : Tu + Tv + Tw + Tz
50/101
Symbol
Tv/2
Tw
Tu
Td
Tv
Tz
f
f : Masterclock Frequency
Delay between beginning of cycle and NRAS Falling Edge
Delay between NRAS Falling Edge and NCAS Falling Edge
Delay between NCAS Falling Edge and NWE Rising Edge
Delay between NWE Rising Edge and end of cycle
Delay between NRAS Falling Edge and address change
Data Valid after beginning of cycle (30 pF)
Parameter
Min.
1/2f
1/f
1/f
32
1/f
1/f
1/f
Typ.
Max.
33
2/f
2/f
1/f
2/f
2/f
1/f
MHz
Unit
ns
ns
ns
ns
ns
ns