stlc5465 STMicroelectronics, stlc5465 Datasheet - Page 42

• Manufacturer Part Number: stlc5465
• Description: Multi Hdlc With Switching Matrix Associated
• Manufacturer: STMicroelectronics

STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
Figure 32 : VCXO Frequency Synchronization
III.8 - Interrupt Controller
III.8.1 - Description
Three external pins are used to manage the inter-
rupts generated by the Multi-HDLC . The interrupts
have three main sources :
- The operating interrupts generated by the HDLC
- The interrupt generated by an abnormal working of
- The non-activity of the microprocessor (Watch-
III.8.2 - Operating Interrupts (INT0 Pin)
There are five main sources of operating interrupts
in the Multi-HDLC circuit :
- The HDLC receiver,
- The HDLC transmitter,
- The CI receiver,
- The Monitor receiver,
- The Monitor transmitter.
When an interrupt is generated by one of these
functions, the interrupt controller :
- Collects all the information about the reasons of
- Stores them in external memory,
- Informs the microprocessor by positioning the
Three interrupt queues are built in external memory
to store the information about the interrupts :
- A single queue for the HDLC receivers and trans-
- One for the CI receivers,
- One for the monitor receivers.
The microprocessor takes the interrupts into ac-
count by reading the Interrupt Register (IR) of the
interrupt controller.
42/101
receivers/transmitters, the CI receivers and the
monitor transmitters/receivers. INT0 Pin is re-
served for this use.
the clock distribution. INT1 Pin is reserved for this use.
dog). WDO Pin is reserved for this use.
this interrupt,
INT0 pin in the high level.
mitters,
This register informs the microprocessor of the
interrupt source. The microprocessor will have in-
formation about the interrupt source by reading the
corresponding interrupt queue (see Paragraph "In-
terrupt Register IR (38)
On an overflow of the circular interrupt queues and
an overrun or underrun of the different FIFO, the
INT0 Pin is activated and the origin of the interrupt
is stored in the Interrupt Register.
A 16 bits register is associated with the Tx Monitor
interrupt. It informs the microprocessor of which
transmitter has generated the interrupt (see Para-
graph "Transmit Monitor Interrupt Register TMIR
(30)
III.8.3 - Time Base Interrupts (INT1 Pin)
The Time base interrupt is generated when an
absence or an abnormal working of clock distribu-
tion is detected. The INT1 Pin is activated.
III.8.4 - Emergency Interrupts (WDO Pin)
The WDO signal is activated by an overflow of the
watchdog register.
III.8.5 - Interrupt Queues
There are three different interrupt queues :
- Tx and Rx HDLC interrupt queue,
- Rx C/I interrupt queue,
- Rx Monitor interrupt queue.
Their length can be defined by software.
For debugging function, each interrupt word of the
CI interrupt queue and monitor interrupt queue can
be followed by a time stamped word. It is composed
of a counter which runs in the range of 250 s. The
counter is the same as the watchdog counter.
Consequently, the watchdog function isn’t available
at the same time.
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