stlc5465 STMicroelectronics, stlc5465 Datasheet - Page 65

• Manufacturer Part Number: stlc5465
• Description: Multi Hdlc With Switching Matrix Associated
• Manufacturer: STMicroelectronics

VII - MICROPROCESSOR TIMING (continued)
VII.7 - 68020 MOD0=0, MOD1=0, MOD2=0
Figure 54 : 68020 Read Cycle
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
Delay NDTACK / NCS0/1 (if t3 > t1), (30pF)
Delay when immediate access
Hold Time Chip Select / NDS rising edge
Delay NDSACK1 / NDS Falling Edge (if t1> t3), (30pF)
Delay when immediate access
Delay NDSACK1 / NDS Rising Edge
Set-up Time Address and R/W/last NDS or NCS
Hold Time Address / NDS
Data valid before NDSACK1 falling edge (30pF)
Data High Impedance after NDS (30pF)
SIZE1/ NUDS
SIZE0/ NLDS
NDSACK0/
NDSACK1/
R/W / NWR
NDS /NRD
NDTACK
NCS0/1
READY
A 0/23
D0/15
NAS /
ALE
Parameter
t5
t1
t3
t7
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
= 5V
= 3.3V
= 5V
= 3.3V
= 5V
= 3.3V
Min.
0
0
0
0
0
0
0
0
0
t6
t4
t8
t2
Typ.
Max.
STLC5465B
108
108
98
98
20
30
15
15
Unit
65/101
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns