stlc5465 STMicroelectronics, stlc5465 Datasheet - Page 79

• Manufacturer Part Number: stlc5465
• Description: Multi Hdlc With Switching Matrix Associated
• Manufacturer: STMicroelectronics

VIII - INTERNAL REGISTERS (continued)
CACL : CYCLICAL ACCESS LIMITED
TC
VIII.10 - Sequence Fault Counter Register - SFCR (12)H
When this register is read by the microprocessor, this register is reset (0000)
F0/15 : FAULT0/15
NB. As the SFCR is reset after reading, a 8-bit microprocessor must read the LSB that will represent the
VIII.11 - Time Slot Assigner Address Register - TAAR (14)H
READ : READ MEMORY
TS0/4 : TIME SLOTS0/4
bit15
bit15
TS4
F15
number of faults between 0 and 255. To avoid overflow escape notice, it is necessary to start counting
at FF00h, by writing this value in SFCR before launching PRSA. If there are more than FFh errors, the
SFCO interrupt bit (see interrupt register IR -38H address) will signal that the fault count register has
reached the value FFFFh (because of the number of faults exceeded 255).
TS3
: Transparent Connection
F14
CACL = 1 (BID is ignored)
If Write Connection Memory, an automatic data write from Connection Memory Data Register
(CMDR) up to 32 locations of Connection Memory occurs. The first location is indicated by OTS
0/4bits of the register (DSTR) related to OTDMq as defined by OM0/2 occurs. The last location
is q +1 F(H).
If Read Connection Memory, an automatic transfer of data from Connection Memory into
Connection Memory Data Register (CMDR) after reading this last by the microprocessor
occurs.The first location is indicated by OTS 0/4 bits of the register (DSTR) related to OTDMq
as defined by OM0/2. The last location is q +1 F(H).
CACL = 0, Write and Read Connection Memory in the normal way.
TC = 1, (BID is ignored), if READ = 0 :
CAC = 0 and CACL = 0. The DSTR bits are taken into account instead of SRCR bits. SRCR bits
are ignored (Destination and Source are identical). The contents of Input time slot i - Input
multiplex j is switched into Output time slot i - Output multiplex j.
CAC = 0 and CACL = 1. Up to 32 "Transparent Connections" are set up.
CAC = 1 and CACL = 0. Up to 256 "Transparent Connections" are set up.
TC = 0, Write and Read Connection Memory are in accordance with BID.
Number of faults detected by the Pseudo Random Sequence analyzer if the analyzer has been
validated and has recovered the receive sequence.
When the Fault Counter Register reaches (00FF)
READ = 1, Read Time slot Assigner Memory.
READ = 0, Write Time slot Assigner Memory.
These five bits define one of 32 time slots in which a channel is set-up or not.
TS2
F13
TS1
F12
TS0
F11
READ
F10
F9
Nu
After reset (0000)
After reset (0100)
bit8
F8
bit8
HDI
bit7
F7
bit7
r
H
H
H
F6
it stays at its maximum value.
e
F5
s
F4
e
H
.
F3
r
F2
v
STLC5465B
F1
e
79/101
bit 0
bit 0
F0
d