stlc5465 STMicroelectronics, stlc5465 Datasheet - Page 74

• Manufacturer Part Number: stlc5465
• Description: Multi Hdlc With Switching Matrix Associated
• Manufacturer: STMicroelectronics

STLC5465B
VIII - INTERNAL REGISTERS (continued)
VIII.8 - Connection Memory Data Register - CMDR (0E)H
This 16 bit register is constituted by two registers :
SOURCE REGISTER (SRCR) and CONTROL REGISTER (CTLR)
SOURCE REGISTER (SRCR) has two use modes depending on CM (bit of CMAR).
CM = 1, access to connection memory (read or write)
- PRSG = 0, ITS 0/4 and IM0/2 bits are defined hereafter :
- PRSG = 1, the Pseudo Random Sequence Generator is validated, SRCR is not significant.
CM = 0, access to data memory (read only). SRC is the data register of the data memory.
CONTROL REGISTER (CTLR) defines each Output Time Slot OTSy of each Output Time Division Multi-
plex OTDMq :
SI
LOOP : LOOPBACK per channel relevant if a bidirectional connection has been established.
OTSV : OUTPUT TIME SLOT VALIDATED
S1/S0 : SOURCE 1/0
74/101
bit15
SCR
ITS 0/4 : Input time slot 0/4 define ITSx with : 0
IM0/2
PS
: SEQUENCE INTEGRITY
SI = 1, the delay is always : (31 - ITSx) + 32 + OTSy.
SI = 0, the delay is minimum to pass through the data memory.
LOOP = 1, OTSy, OTDMq is taken into account instead of ITSy, ITDMq.
OTSV = 1, transparent Mode LOOPBACK.
OTSV = 0, not Transparent Mode LOOPBACK.
OTSV = 1, OTSy OTDMq is enabled.
OTSV = 0, OTSy OTDMq is High Impedance.
(OTSy : Output Time slot with 0 y 31; OTDMq : Output Time Division Multiplex with 0 q 7).
Note:
Connection
Release
PRSA
S1
CONTROL REGISTER (CTLR)
0
0
1
1
: Input Time Division Multiplex 0/2 define ITDMp with : 0
When the source of D channels is selected (GCI channels defined by ITS 1/0) and when
the destination is selected (Output timeslot defined by OTS 0/4; output TDM defined by
OM 0/2) the upstream connection is set up; the downstream connection (reverse
direction TDM to GCI) is set up automatically if ITS 2 bit is at 1. So BID, bit of CMAR
must be written at”0”.
Remember: write S1=1, S0=0 and ITS 2 bit = 0 to release the downstream connection;
the upstream connection is released when the source changes.
S0
S1
0
1
0
1
Source for each timeslot of DOUT0/7
Data Memory (Normal case)
Connection Memory
D channels from/to GCI multiplexes (See note and table hereafter)
Pseudo Random Sequence Generator delivers Hyperchannel at n x 64Kb/s is possible.
S0
OTSV LOOP
After reset (0000)
bit8
SI
IM2
bit7
x
H
31;
IM1
SOURCE REGISTER (SRCR)
IM0
ITS 4 ITS 3 ITS 2 ITS 1 ITS 0
p
7.
bit 0