W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 33

• Manufacturer Part Number: W90221X
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

NTD#/WGLBCS# (output)
5.10.3 Application Notes
WIO bus is designed to connect ISA-like, low speed devices such as code-ROM, Flash and 8-
/16-bit IO devices. The WIO controller itself is a PCI slave device, if the address and access
type of any PCI cycle match the WIOBASE or XMBASE[8:15] of WIO, the WIO controller
responds the DEVSEL# and TRDY# to PCI bridge and generate correspond WIO bus signals
to WIO devices in the "data phase" of current PCI cycle.
XMBASE[7] will be set right from chip reset, all PCI cycles will be treated as WIO access and
all code read (PCI cycles) will return data from WIO bus. After the memory (XMBASE) and IO
(WIOBASE) have been properly configured, XMBASE[7] shall be set logic low immediately to
avoid possible wrong response from WIO controller.
Because WROMCS#, WIOCS#, WRD# and WWR# share the same pins with COMBE[0:3] of
PCI bus, they might toggle during any PCI cycles. It is necessary to OR these control signals
with INTD#, which serves as "WIO global chip-select" dedicatedly, before they reaching the
WIO devices.
The following figures show some typical timing diagrams of WIO command cycles:
Figure 5.10.3.1 Fastest WIO I/O read cycle (0 wait)
W90221X version 0.6
PCI cycles:
WIO cycles:
PCICLK
FRAME#
DEVSEL#
TRDY#
PDA[31:24]
PDA[23:8]
PDA[7:0]
INTD#
COMBE_3#
COMBE_2#
COMBE_1#
COMBE_0#
16-bit IO address
command cycle is ongoing.
If WIO is enable, this signal shall not connect to any PCI bus
master.
Asserted low indicating a WIO command cycle is ongoing.
High byte data
Low byte data
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