W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 17

• Manufacturer Part Number: W90221X
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

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5.2 Power-on Settings
MD[31]
MD[28-30]
MD[26-27]
MD[25]
MD[24]
MD[20-23]
CTM[0-3]
W90221X version 0.6
Optional SCLK input for SSI interface as SSI operation in slave mode
Video-Accelerator clock (27MHz, 13.5MHz)
system clock (CPU-clock/2, /3, /4)
SDRAM clock (CPU-clock/1, /1.5, /2)
UART, Timer clock (13.5MHz)
MD[28:30]
MD[26:27]
MD[20:23]
MD Bit(s)
MD[31]
MD[25]
MD[24]
Speed of Internal System Clock Signal (CPUCLK)
Speed of Internal PCI Clock Signal (EXTCLK)
Mode of Synchronous Serial Interface
Speed of internal OSC Clock Signal
pulled high to enable internal PLL unit
used to choose CPUCLK from 80MHz to 110MHz
used to choose EXTCLK (PCICLK)
pulled high to set X_SCLK (of SSI unit) to output mode (SCLK
master mode)
set high to choose OSC clock as GFXCLK/2
reserved for future use
(0xf00001d8) memorize states of MD[20-23] during power-on interval
(Firmware reads these bits to know what kind of target board is
Reserved for Future Use
Status of Internal PLL
[1, 1, 1]:
[1, 1, 0]:
[1, 0, 1]:
[1, 0, 0]:
DX3 Mode:
DX4 Mode:
DX5 Mode:
DX6 Mode:
Value
111
110
101
NA
00
01
10
11
0
1
0
1
0
1
80 MHz
90 MHz
100 MHz
110 MHz
2'b00 to choose 1/3 CPUCLK,
2'b01 to choose 1/4 CPUCLK,
2'b10 to choose 1/5 CPUCLK,
2'b10 to choose 1/6 CPUCLK
CPUCLK / 3
CPUCLK / 4
CPUCLK / 5
CPUCLK / 6
GFXCLK / 2
DPCLK / 2
100 MHz
80 MHz
90 MHz
Setting
Disable
Enable
Master
Slave
NA
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