W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 10

• Manufacturer Part Number: W90221X
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

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The following tables provide a brief description of each pin on the W9961CF. The
following signal type definitions are used in these descriptions:
I
I/O
O
TS
OC
AO
AI
RESET
DPCLK
GFXCLK
GPIO[0:7]
GPIO[8]
GPIO[9]
GPIO[10]
GPIO[11]
W90221X version 0.6
PIN Name
Pin Description
Input pin
Bi-directional input/output pin
Output pin
Tri-State output pin
open-collector pin
analog output pin
analog input pin
TYPE
I/O
I/O
I/O
I/O
I/O
I
I
I
138-145
PIN #
199
146
148
149
150
96
8
System Reset and Clock
General Purpose I/O
CPU Power-On reset input, high active
This clock source serves as internal PLL input as well as
VA's system clock. A precise 27MHz clock source shall be
connected to this pin during normal operation.
This clock source serves as pixel clock, 36MHz to 50MHz,
using in 800x600 non-interlace monitor. For TV subsystem,
this clock may pull high or low externally. Meanwhile,
GFXCLK may also serves as system OSC (for baud rate or
timer adjustment), if MD[24] is pull high externally.
If parallel port is enabled (port 0x3e[4] = 1), these pins serve
as bi-directional ECP data bus "ED[0:7] " with ED[0] the most
significant bit (In/Out).
If parallel port is not enabled (port 0x3e[4:5] = 0x), these pins
provide general purpose I/O function (In/Out).
If parallel port is enabled (port 0x3e[4:5] = 1x), this pin serves
as ECP "nInit" (output).
If parallel port is not enabled (port 0x3e[4:5] = 0x), this pin
provides general purpose I/O function (In/Out)
If parallel port is enabled (port 0x3e[4:5] = 1x), this pin serves
as ECP “ nSelectIn" (output).
If parallel port is not enabled (port 0x3e[4:5] = 0x), this pin
provides general purpose I/O function (In/Out)
If parallel port is enabled (port 0x3e[4] = 1x), this pin serves
as ECP “ Select" (input).
If parallel port is not enabled (port 0x3e[4:5] = 00), this pin
provides general purpose I/O function (In/Out).
During "clock test" mode (port 0x3e[4] = 01), this pin outputs
internal CPUCLK (output).
If parallel port is enabled (port 0x3e[4] = 1x), this pin serves
as ECP "PError" (input).
If parallel port is not enabled (port 0x3e[4:5] = 00), this pin
provides general purpose I/O function (In/Out).
During "clock test" mode (port 0x3e[4] = 01), this pin outputs
internal MCLK_CTL (output).
DESCRIPTION
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