W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 141

• Manufacturer Part Number: W90221X
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

Configuration Register (CFG)
Port address: 0xf0000360
Bit 0
Bits 1-3
Bits 4-6
Bits 7-9
Bits 10-11
Bit 12-13
Bits 14-15
W90221X version 0.6
IOen
ROMRext[1:2]
0
8
0
1
1
9
WIO I/O space enable (I/O devices connected on this WIO bus will
only be enabled by turning on this bit)
I/O space disable
I/O space enable
I/O read/write command wait state
These three bits define the wait states of I/O read or write commands
appeared on the WIO bus. The I/O read or write commands will be
active for "CFG[1:3] + 2" PCICLK cycles.
Memory (Flash) write command wait state
These three bits define the wait states of memory write commands
appeared on the WIO bus. The memory write commands will be
active for "CFG[4:6] + 2" PCICLK cycles.
Memory (ROM/Flash) read command wait state
These three bits define the wait states of memory read commands
appeared on the WIO bus. The memory read commands will be active
for "CFG[7:9] + 2" PCICLK cycles.
Command setup time
These two bits define the address-to-command setup time of all
command cycles as well as the data-to-command setup time of all
write cycles. The setup time is "CFG[10:11] + 2" PCICLK cycles
immediately preceding the falling edge of RD_/WR_ signals.
Command hold time
These two bits define the address/data-to-command hold time of write
cycles. The hold time is "CFG[12:13] + 2" PCICLK cycles immediately
following the rising edge of WR_ signal. As for read cycles, the
minimum data hold time requirement is zero.
Consecutive ROM read command recovery time
For Flash/ROM read cycles, the WIO supports only 32-bit access.
The WIO controller will automatically convert the memory word
access into four consecutive byte accesses, and the latency between
consecutive RD_ cycles will be "CFG[14:15] + 2" PCICLK cycles.
IOext[0:2]
10
2
CMDset[0:1]
Access type: read/write
11
3
12
CMDhold[0:1]
4
ROMWext[0:2]
13
5
14
6
CMDrec[0:1]
Default: 0x0
ROMRext[0]
15
7
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