W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 12

• Manufacturer Part Number: W90221X
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

INTA#, INTB#,
INTC#
REQ0#,
REQ1#
GNT0#
GNT1#
PCIRST#
PCICLK
SERR#
PERR#
STOP#
TRDY#
DEVSEL#
FRAME#
IRDY#
W90221X version 0.6
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
I
36, 35, 33
102, 101
104, 103
23
21
67
68
69
71
70
74
72
PCI Interrupt input, level sensitive, low active signal. Once
the INTx# signal is asserted, it remains asserted until the
device driver clear the pending request. When the request is
cleared, the device de-asserts its INTx# signal.
PCI Request input, indicates to the PCI arbiter that this agent
desires use of the bus.
PCI Grant output, indicates to the agent that access to the
bus has been granted.
PCI Reset output, is used to bring PCI-specific registers,
sequencers, and signals to a consistent state. Low active.
PCI Clock output, provides timing for all transactions on PCI
and is an input to every PCI device.
PCI System Error is for reporting address parity errors, data
parity errors on the Special Cycle command, or any other
system error where the result will be catastrophic. The
assertion of SERR# is synchronous to the clock and meets
the setup and hold times of all bused signals.
PCI Parity Error is only for the reporting of data parity errors
during all PCI transactions except a Special Cycle. The
PERR# pin is sustained tri-state and must be driven active by
the agent receiving data two clocks following the data when a
data parity error is detected. The minimum duration of
PERR# is one clock for each data phase that a data parity
error is detected. An agent cannot report a PERR# until it has
claimed the access by asserting DEVSEL# (for a target) and
completed a data phase or is the master of the current
transaction.
PCI Stop indicates the current target is requesting the master
to stop the current transaction.
PCI Target Ready indicates the selected device
complete the current data phase of the transaction. A data
phase is completed on any clock both TRDY# and IRDY# are
sampled asserted. During a read, TRDY# indicates that valid
data is present on PDA[31:0]. During a write, it indicates the
target is prepared to accept data. Wait cycles are inserted
until both IRDY# and TRDY# are asserted together.
PCI Device Select, when actively driven, indicates the driving
device has decoded its address as the target of the current
access. As an input, DEVSEL# indicates whether any device
on the bus has been selected.
PCI Cycle Frame is driven by the current master to indicate
the beginning and duration of an access. FRAME# is
asserted to indicate a bus transaction is beginning. While
FRAME# is asserted, data transfers continue. When FRAM#
is de-asserted, the transaction is in the final data phase or
has completed.
PCI Initiator Ready indicates the bus master
complete the current data phase of the transaction. A data
phase is completed on any clock both IRDY# and TRDY# are
sampled asserted. During a write, IRDY# indicates that valid
data is present on PDA[31:0]. During a read, it indicates the
master is prepared to accept data. Wait cycles are inserted
until both IRDY# and TRDY# are asserted together.
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