W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 14

• Manufacturer Part Number: W90221X
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

VREF
COMP
RSET
EXTVREF
CS0L#/RAS0#,
CS1L#/RAS1#
CS0H#, CS1H#
RAS#, CAS#
WE#
CAS[0:3]#/
DQMB[0:3]
MA[0:13]
MD[0:31]
CKE
MCLK
W90221X version 0.6
AO
AO
AO
I/O
AI
O
O
O
O
O
O
O
O
28, 29, 30, 31
157-162, 164,
166-173, 175,
177-184, 186,
6, 10, 16, 25
3, 4, 5, 11,
12, 13, 14,
15, 26, 27,
195, 197
201, 203
205, 206
188-194
125
127
126
123
204
17
19
Memory Controller Interface
Voltage Reference Output. Bypass and decouple the voltage
reference with a 0.1uF ceramic capacitor to the VDDa.
The decoupling capacitor shall be as close to this pin as
possible. This pin as well as "COMP" is used to control the
current of internal current sources to be exactly equal to
"Iref".
Compensation pin. It shall be decoupled with a 0.1uF
ceramic capacitor to VDDa. The decoupling capacitor shall
be as close to this pin as possible.
Current Source Adjusting Resistor. This pin is used to adjust
the full-scale current of TV's analog outputs. A resistor shall
be connected between this pin and VSSa. The Iref is
approximate to 1.16V/RSET (The current mirror of DAC's
"Iref" is adjusted by this pin).
External Vref input. This signal supplies the DAC's "bandgap"
output from an external 1.235V voltage source. A 0.1uF
bypass capacitor shall be always connected between this pin
and VDDa. (The "bandgap" is an voltage stabilizer of voltage-
reference-generator "Vref"). This pin may be left
unconnected.
During EDO mode, these signals are served as RAS0#,
RAS1# that used to latch the row address MA[0:11] lines into
the DRAM. Each signal is used to select one DRAM bank.
During SDRAM mode, these signals are served as CS0L#,
CS1L# that indicates the command decoder is enable or
disable.
Similar to CS0L#/CS1L#, when on-board SDRAM is used,
These pins are NC pins. When SDRAM DIMM module is
used, these signals indicates current cycle accessing the
high word (32 bits) of DIMM's data bus (double words).
This signals along with WE# and CS# define the command
code of SDRAM configuration cycles.
This signal asserted to indicate a write cycle to DRAM.
In EDO mode: these signals are served as CAS# function
and used to latch the column address (MA[0:11]) into
DRAMs. It also indicates which bytes can be accessed.
In SDRAM mode: these signals are served as DQMB
function, these are input mask signals for write cycle and
output enable signals for read cycle.
These signals are used to provide the multiplexed row and
column address to the EDO DRAM or SDRAM.
These signals are used to interface to the DRAM data bus.
This signal is used to enable or disable MCLK into SDRAM.
This signal is SDRAM clock input, all SDRAM input /output
signals are referenced with MCLK rising edge.
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