W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 18

• Manufacturer Part Number: W90221X
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

DRAMTCtrl2[2-3]
TVTWH[12-15]
VPTC[17]
5.2.1 Related Pins
DPCLK (input)
VCLK (input)
GFXCLK (input)
SCLK (in/out)
VDDl, VSSl:
5.3 Operation Modes
¨
W90221X version 0.6
Normal Mode (PLL is enable)
This clock source serves as internal PLL input as well as VA's system clock. A precise
27MHz clock source shall be connected to this pin during normal operation.
This clock source serves as VMI bus pixel clock (27MHz). A precise 27MHz
clock source shall be connected to this pin.
This clock source serves as pixel clock, 36MHz to 50MHz, using in 800x600 non-interlace
monitor. For TV system, this clock may pull high or low externally. Meanwhile, FXCLK may
also serve as system OSC (for baud rate or timer adjustment), if MD[24] is pull high externally.
This pin is the serial bit clock between SSI and codec device. The SCLK may be input
or output depending on whether SSI is operated in slave- or master-mode.
Dedicated power/ground pins for internal PLL unit. VDDl shall be connected to a 3.3V
voltage source.
TV system
Monitor
DPCLK = 27MHz
VCLK = 27MHz
GFXCLK may be unconnected
PCLK = DPCLK/2 = 13.5MHz
PLLin = DPCLK/2 = 13.5MHz
CPUCLK = 80 ~ 100MHz
EXTCLK = CPUCLK/3, CPUCLK/4, CPUCLK/5, CPUCLK/6
MCLK = CPUCLK/1, CPUCLK/1.5, CPUCLK/2
OSC = DPCLK/2 = 13.5MHz
DPCLK = 27MHz
VCLK = 27MHz
GFXCLK = 36.864MHz (for deriving 18.432MHz OSC)
PCLK = GFXCLK = 36.864MHz
PLLin = DPCLK/2 = 13.5MHz
CPUCLK = 80 ~ 100MHz
= GFXCLK/2 = 18.432MHz
operating.)
(0xf000003e) defines MCLK frequencies
(0xf0000178) defines the format of video output
(0xf000017c) defines the direction of 8-bit video-in bus
MX1 Mode:
MX1.5 Mode:
MX2 Mode:
2'b00 to choose 1/3 CPUCLK,
2'b01 to choose 1/4 CPUCLK,
2'b10 to choose 1/5 CPUCLK,
(MD[24] = 0 on power-on reset)
(MD[24] = 1 on power-on reset)
- 18 -