AT32UC3C0128C Atmel Corporation, AT32UC3C0128C Datasheet - Page 979

• Manufacturer Part Number: AT32UC3C0128C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0128C

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Table 33-2.
32117C–AVR-08/11
Period Value
(
Dead-Time Values
(
Duty-Cycle Values
(
Update Period Value
(
CPRDUPDx)
DTUPDx)
CDTYUPDx)
SCUPUPD)
Summary of the update of registers of Synchronous Channels
Update is triggered at the next
PWM period as soon as the
UPDULOCK bit is set to 1
33.6.2.10 on page
a comparison match (see
the SCM register.
Write by the CPU
Not applicable
Not applicable
UPDM=0
983). The user can choose to synchronize the PDCA transfer request with
Section 33.6.3 on page
the UPDULOCK bit is set to 1
the UPDULOCK bit is set to 1
next PWM period as soon as
next PWM period as soon as
Update is triggered at the
Update is triggered at the
Write by the CPU
Write by the CPU
Write by the CPU
UPDM=1
PWM period as soon as the update period
PWM period as soon as the update period
counter has reached the value UPR
counter has reached the value UPR
Update is triggered at the next
Update is triggered at the next
986), by the PTRM and PTRCS fields in
Write by the CPU
Write by the PDCA
AT32UC3C
UPDM=2
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