AT32UC3C0128C Atmel Corporation, AT32UC3C0128C Datasheet - Page 1206

• Manufacturer Part Number: AT32UC3C0128C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0128C

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

39.4.5.1
39.4.5.2
39.4.5.3
39.4.6
32117C–AVR-08/11
JTAG Interface
I/O Lines
Power Management
Clocks
The TMS, TDI, TDO, and TCK pins are multiplexed with I/O lines. When the JTAG is used the
associated pins must be enabled. To enable the JTAG pins, refer to
While using the multiplexed JTAG lines all normal peripheral activity on these lines is disabled.
The user must make sure that no external peripheral is blocking the JTAG lines while
debugging.
When an instruction that accesses the SAB is loaded in the instruction register, before entering
a sleep mode, the system clocks are not switched off to allow debugging in sleep modes. This
can lead to a program behaving differently when debugging.
The JTAG Interface uses the external TCK pin as clock source. This clock must be provided by
the JTAG master.
Instructions that use the SAB bus requires the internal main clock to be running.
The JTAG Interface is accessed through the dedicated JTAG pins shown in
1205. The TMS control line navigates the TAP controller, as shown in
The TAP controller manages the serial access to the JTAG Instruction and Data registers. Data
is scanned into the selected instruction or data register on TDI, and out of the register on TDO,
in the Shift-IR and Shift-DR states, respectively. The LSB is shifted in and out first. TDO is high-
Z in other states than Shift-IR and Shift-DR.
The device implements a 5-bit Instruction Register (IR). A number of public JTAG instructions
defined by the JTAG standard are supported, as described in
ber of 32-bit AVR-specific private JTAG instructions described in
instruction selects a specific data register for the Shift-DR path, as described for each
instruction.
Section
Section
Figure 39-6 on page
39.5.2, as well as a num-
Section
AT32UC3C
Table 39-6 on page
39.4.7.
39.5.3. Each
1207.
1206