AT32UC3C0128C Atmel Corporation, AT32UC3C0128C Datasheet - Page 898

• Manufacturer Part Number: AT32UC3C0128C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0128C

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32.6.3.12
32117C–AVR-08/11
RXINI
FIFOCON
IN
Management of OUT pipes
• Multi packet mode for IN pipes
• Overview
• Detailed description
(bank 0)
DATA
RXINI
FIFOCON
RXINI should always be cleared before clearing FIFOCON to avoid missing an RXINI event.
Figure 32-19. Example of an IN pipe with one data bank
Figure 32-20. Example of an IN pipe with two data banks
See
IN pipe.
OUT packets are sent by the host. All the data can be written, acknowledging whether or not the
bank is full.
The pipe and its descriptor in RAM must be pre configured.
When the current bank is clear, the Transmitted OUT Data Interrupt (TXOUTI) and FIFO Control
(UPSTAn.FIFOCON) bits will be set simultaneously. This triggers a PnINT interrupt if the Trans-
mitted OUT Data Interrupt Enable bit (UPCONn.TXOUTE) is one.
IN
”Multi packet mode for OUT endpoints” on page 889
ACK
HW
(bank 0)
DATA
SW
read data from CPU
BANK 0
ACK
HW
SW
SW
read data from CPU
IN
BANK 0
IN
(bank 1)
DATA
(bank 0)
DATA
and just replace OUT endpoints with
SW
ACK
HW
ACK
HW
AT32UC3C
read data from CPU
read data from CPU
SW
SW
BANK 1
BANK 0
898