AT32UC3C0128C Atmel Corporation, AT32UC3C0128C Datasheet - Page 940

• Manufacturer Part Number: AT32UC3C0128C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0128C

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32.7.3
32.7.3.1
Register Name:
Access Type:
Offset:
Reset Value:
•
•
• RESUME: Send USB Resume
• RESET: Send USB Reset
• SOFE: Start of Frame Generation Enable
32117C–AVR-08/11
31
23
15
7
-
-
-
-
Writing a zero to this bit has no effect.
Writing a one to this bit will generate a USB Resume on the USB bus. This bit should only be done when the start of frame
generation is enabled (SOFE bit is one).
This bit is cleared when the USB Resume has been sent or when a USB reset is requested.
Writing a zero to this bit might be useful when a device disconnection is detected (UHINT.DDISCI is one) while a USB Reset is
being sent.
Writing a one to this bit will generate a USB Reset on the USB bus.
This bit is cleared when the USB Reset has been sent.
Writing a zero to this bit will disable the SOF generation and to leave the USB bus in idle state.
Writing a one to this bit will generate SOF on the USB bus in full speed mode and keep it alive in low speed mode.
This bit is set when a USB reset is requested or an upstream resume interrupt is detected (UHINT.RXRSMI).
USB Host Registers
Host General Control Register
30
22
14
6
-
-
-
-
UHCON
Read/Write
0x0400
0x00000000
29
21
13
5
-
-
-
-
28
20
12
4
-
-
-
-
27
19
11
3
-
-
-
-
RESUME
26
18
10
2
-
-
-
RESET
25
17
9
1
-
-
-
AT32UC3C
SOFE
24
16
8
0
-
-
-
940