AT32UC3C0128C Atmel Corporation, AT32UC3C0128C Datasheet - Page 348

• Manufacturer Part Number: AT32UC3C0128C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0128C

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.3
Figure 19-1. SDRAM Controller Block Diagram
19.4
32117C–AVR-08/11
C on tro ller
M an ag er
M e m o ry
P o w e r
Block Diagram
I/O Lines Description
C LK _ S D R A M C
C hip S elect
S D R A M C
S D R A M C
Inte rru pt
Table 19-1.
Name
SDCK
SDCKE
SDCS
BA[1:0]
RAS
CAS
SDWE
P e riph era l B us
S D R A M C
U ser Interfa ce
I/O Lines Description
Description
SDRAM Clock
SDRAM Clock Enable
SDRAM Chip Select
Bank Select Signals
Row Signal
Column Signal
SDRAM Write Enable
S D R A M C _ A [1 2:1 1]
S D R A M C _A [9:0 ]
S D R A M C _A [10 ]
D [15:0]
S D C K
S D C K E
B A [1:0]
S D C S
D Q M [0]
D Q M [1 ]
R A S
C A S
S D W E
M U X L og ic
E B I
C o ntroller
Type
Output
Output
Output
Output
Output
Output
Output
I/O
AT32UC3C
Active Level
High
Low
Low
Low
Low
S D C K E
N C S [1]
A D D R [1 7:16 ]
C A S
R A S
S D W E
A D D R [1 1:2]
S D A 10
A D D R [1 3:14 ]
A D D R [0 ]
D A T A [1 5:0]
S D C K
N W E 1
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