IDT82P2816BB IDT, Integrated Device Technology Inc, IDT82P2816BB Datasheet - Page 61

• Manufacturer Part Number: IDT82P2816BB
• Description: IC LIU T1/J1/E1 16+1CH 416-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P2816BB

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Defect and Alarm Detection, Driver Over-Current Detection and Protection, LLOS Detection, PRBSARB / IB Detection and Generation
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Power (watts): -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2816BB

3.6.3
should be a clock with +/-32 ppm (in T1/J1 mode) or +/-50 ppm (in E1
mode) accuracy. The clock frequency of MCLK is set by pins
MCKSEL[3:0] and can be N x 1.544 MHz or N x 2.048 MHz with 1 ≤ N ≤
8 (N is an integer number). Refer to MCKSEL[3:0] pin description for
details.
device will enter power down. In this case, both the receive and transmit
circuits are turned off. The pins on the line interface will be in High-Z
state. The pins on receive system interface will be in High-Z state or in
low level, as selected by the RHZ bit (b6, RCF0,...). The input on the
Functional Description
IDT82P2816
MCLK provides a stable reference timing for the IDT82P2816. MCLK
If there is a loss of MCLK (duty cycle is less than 30% for 10 µs), the
MCLK, MASTER CLOCK INPUT
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
61
transmit system interface is ignored and the output on the transmit
system interface will be in High-Z state. Refer to Section 3.2.7 Receiver
Power Down and Section 3.3.7 Transmitter Power Down for details.
matically.
3.6.4
MHz in T1/J1 mode or 2.048 MHz in E1 mode. XCLK is used as select-
able reference clock for
If MCLK recovers after loss of MCLK the device will be reset auto-
XCLK is derived from MCLK. For the respective channel, it is 1.544
• pattern /AIS generation
• RCLKn in LLOS
• Loss of TCLKn to determine Transmit Output High-Z.
XCLK, INTERNAL REFERENCE CLOCK INPUT
February 6, 2009